| Presentation | 2019-10-24 Low temperature formation of PdErSi/Si(100) for Schottky barrier source and drain MOSFET applications Rengie Mark D. Mailig, Yuichiro Aruga, Min Gee Kim, Shun-ichiro Ohmi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, the effects of the TiN encapsulating layer on the low temperature formation of the PdErSi/Si(100) with dopant segregation (DS) process was investigated. To control the profile of the dopants before the DS process, the thickness of the TiN encapsulating layer was varied from 0 to 30 nm. This is to increase the number of segregated dopants along the interface after the DS process. Low SBH for hole of 0.20 eV with ideality factor of 1.08 for samples 25 nm TiN on 20 nm PdEr was realized. It was also found that the interface qualities of the PdErSi/Si(100) were improved by utilizing the TiN encapsulating layer as shown by the reduction of the density of interface states to 10-11 eV-1cm-2. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PdEr-Silicide / Dopant Segregation Process / Schottky Barrier Height / TiN Encapsulating Layer |
| Paper # | SDM2019-61 |
| Date of Issue | 2019-10-16 (SDM) |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2019/10/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Niche, Tohoku Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Process Science and New Process Technology |
| Chair | Takahiro Shinada(Tohoku Univ.) |
| Vice Chair | Hiroshige Hirano(TowerJazz Panasonic) |
| Secretary | Hiroshige Hirano(Shizuoka Univ.) |
| Assistant | Takahiro Mori(AIST) / Nobuaki Kobayashi(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low temperature formation of PdErSi/Si(100) for Schottky barrier source and drain MOSFET applications |
| Sub Title (in English) | |
| Keyword(1) | PdEr-Silicide |
| Keyword(2) | Dopant Segregation Process |
| Keyword(3) | Schottky Barrier Height |
| Keyword(4) | TiN Encapsulating Layer |
| 1st Author's Name | Rengie Mark D. Mailig |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Yuichiro Aruga |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Min Gee Kim |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 4th Author's Name | Shun-ichiro Ohmi |
| 4th Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2019-10-24 |
| Paper # | SDM2019-61 |
| Volume (vol) | vol.119 |
| Number (no) | SDM-239 |
| Page | pp.pp.39-43(SDM), |
| #Pages | 5 |
| Date of Issue | 2019-10-16 (SDM) |