Presentation 2019-11-14
Ferroelectric FET-based Parallel Product-Sum Operation Neuromorphic Circuits
Koki Kamimura, Susumu Nohmi, Ken Takeuchi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In recent years, Moore’s Law which has supported the improvement of semiconductor performance is coming to an end. Therefore, neuromorphic computing has attracted attention instead of conventional von Neumann computing. Among neuromorphic computing, neuromorphic circuits using non-volatile memory have particularly attracted attention. However, conventional neuromorphic circuits are small range of weight and high power consumption. This paper proposes neuromorphic circuits using ferroelectric-FET (FeFET). FeFET is a kind of non-volatile memory and has feature that the dynamic range of cell current is wide. Therefore, the range of weight is also wide. In addition, proposed neuromorphic circuits achieve low power consumption and a number of product-sum operations in parallel.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FeFET / Neuromorphic / Dynamic range of cell current / Parallel product-sum operation
Paper # ICD2019-31,IE2019-37
Date of Issue 2019-11-07 (ICD, IE)

Conference Information
Committee VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2019/11/13(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Ehime Prefecture Gender Equality Center
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2019 -New Field of VLSI Design-
Chair Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.)
Vice Chair Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.)
Secretary Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK)
Assistant Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Ferroelectric FET-based Parallel Product-Sum Operation Neuromorphic Circuits
Sub Title (in English)
Keyword(1) FeFET
Keyword(2) Neuromorphic
Keyword(3) Dynamic range of cell current
Keyword(4) Parallel product-sum operation
1st Author's Name Koki Kamimura
1st Author's Affiliation Chuo University(Chuo Univ.)
2nd Author's Name Susumu Nohmi
2nd Author's Affiliation Chuo University(Chuo Univ.)
3rd Author's Name Ken Takeuchi
3rd Author's Affiliation Chuo University(Chuo Univ.)
Date 2019-11-14
Paper # ICD2019-31,IE2019-37
Volume (vol) vol.119
Number (no) ICD-284,IE-285
Page pp.pp.13-17(ICD), pp.13-17(IE),
#Pages 5
Date of Issue 2019-11-07 (ICD, IE)