| Presentation | 2019-11-14 A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability and to maintain the high fault efficiency. To solve the challenge, a design-for-testability method for a stuck-at-faults using partial scan design and controller augmentation to execute the operations of easily testable functional k-time expansion models was proposed. In the partial scan design, state registers in controllers are replaced with scan registers. As the results, test generation is freely able to transfer to any invalid states of controllers by shifting operations. High fault efficiency was achieved by designing state transitions of invalid states such that hardware elements in a data-path circuits become testable. In this paper, we propose a method to generate easily testable functional k-time expansion models for transition faults based on the conventional design-for-testability method to reduce the area overhead and test application time and to maintain fault efficiency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Easily testable functional k-time expansion models / Controller augmentation / Partial scan design / k-cycle capture testing / Transition faults |
| Paper # | VLD2019-43,DC2019-67 |
| Date of Issue | 2019-11-06 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
|---|---|
| Conference Date | 2019/11/13(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Prefecture Gender Equality Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
| Chair | Nozomu Togawa(Waseda Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Yuichiro Shibata(Nagasaki Univ.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Yutaka Tamiya(Fujitsu Lab.) / / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Daisuke Fukuda(Fujitsu Labs.) / Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Kentaro Sano(RIKEN) / Yoshiki Yamaguchi(Tsukuba Univ.) / Masafumi Takahashi(Toshiba-memory) / Kazuya Kodama(NII) / Keita Takahashi(Nagoya Univ.) |
| Secretary | Daisuke Fukuda(Univ. of Aizu) / Hiroshi Takahashi(Hitachi) / Michihiro Koibuchi(Nihon Univ.) / Kota Nakajima(Chiba Univ.) / Kentaro Sano(Nagoya Inst. of Tech.) / Yoshiki Yamaguchi(Hokkaido Univ.) / Masafumi Takahashi(Hiroshima City Univ.) / Kazuya Kodama(e-trees.Japan) / Keita Takahashi(Tohoku Univ.) / (Socionext) / (NTT) / (NHK) |
| Assistant | Kazuki Ikeda(Hitachi) / / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) / Kyohei Unno(KDDI Research) / Norishige Fukushima(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs |
| Sub Title (in English) | |
| Keyword(1) | Easily testable functional k-time expansion models |
| Keyword(2) | Controller augmentation |
| Keyword(3) | Partial scan design |
| Keyword(4) | k-cycle capture testing |
| Keyword(5) | Transition faults |
| 1st Author's Name | Yuta Ishiyama |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Yuki Ikegaya |
| 3rd Author's Affiliation | Nihon University(Nihon Univ.) |
| Date | 2019-11-14 |
| Paper # | VLD2019-43,DC2019-67 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-282,DC-283 |
| Page | pp.pp.133-138(VLD), pp.133-138(DC), |
| #Pages | 6 |
| Date of Issue | 2019-11-06 (VLD, DC) |