Presentation 2019-10-12
LSI Implementation and Its Evaluation of an Izhikevich Model Neuron Analog MOS Circuit
Yuki Tamura, Satoshi Moriya, Tatsuki Kato, Masao Sakuraba, Shigeo Sato, Yoshihiko Horio,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The Izhikevich neuron model, which can reproduce various spike activities with a small amount of calculation, is indispensable to construct a new neuromorphic hardware for high order and low power information processing like biological neural network. In the previous report, we proposed a new Izhikevich model neuron circuit based on the discrepancies between the Izhikevich neuron model and the Izhikevich model neuron circuit proposed by Wijekoon and Dudek in 2008, and investigated the dynamics of our proposed circuit by phase plane analysis and SPICE simulation. In this research, we implemented our proposed circuit on an LSI chip using 65nm CMOS technology and compared its dynamics with that of SPICE simulation. By LSI chip measurement, we successfully observed four types of spikes as expected.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Izhikevich Neuron Model / Analog Neuron Circuit / SPICE Simulation / Phase Plane Analysis / Analog LSI
Paper # MBE2019-44,NC2019-35
Date of Issue 2019-10-04 (MBE, NC)

Conference Information
Committee MBE / NC
Conference Date 2019/10/11(2days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Taishin Nomura(Osaka Univ.) / Hayaru Shouno(UEC)
Vice Chair Takashi Watanabe(Tohoku Univ.) / Kazuyuki Samejima(Tamagawa Univ)
Secretary Takashi Watanabe(Kyushu Univ.) / Kazuyuki Samejima(NAIST)
Assistant Yasuyuki Suzuki(Osaka Univ.) / Akihiro Karashima(Tohoku Inst. of Tech.) / Takashi Shinozaki(NICT) / Ken Takiyama(TUAT)

Paper Information
Registration To Technical Committee on ME and Bio Cybernetics / Technical Committee on Neurocomputing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) LSI Implementation and Its Evaluation of an Izhikevich Model Neuron Analog MOS Circuit
Sub Title (in English)
Keyword(1) Izhikevich Neuron Model
Keyword(2) Analog Neuron Circuit
Keyword(3) SPICE Simulation
Keyword(4) Phase Plane Analysis
Keyword(5) Analog LSI
1st Author's Name Yuki Tamura
1st Author's Affiliation Tohoku University(Tohoku Univ.)
2nd Author's Name Satoshi Moriya
2nd Author's Affiliation Tohoku University(Tohoku Univ.)
3rd Author's Name Tatsuki Kato
3rd Author's Affiliation Tohoku University(Tohoku Univ.)
4th Author's Name Masao Sakuraba
4th Author's Affiliation Tohoku University(Tohoku Univ.)
5th Author's Name Shigeo Sato
5th Author's Affiliation Tohoku University(Tohoku Univ.)
6th Author's Name Yoshihiko Horio
6th Author's Affiliation Tohoku University(Tohoku Univ.)
Date 2019-10-12
Paper # MBE2019-44,NC2019-35
Volume (vol) vol.119
Number (no) MBE-224,NC-225
Page pp.pp.69-73(MBE), pp.69-73(NC),
#Pages 5
Date of Issue 2019-10-04 (MBE, NC)