| Presentation | 2019-08-07 [Invited Talk] A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The main feature of this processor is its inter-chip connection interface for making a larger chip. A credit card sized compute node integrating two CMOS-APs was also developed as an interface with existing computer systems. The compute node can handle up to 61,952 spins at a time. A performance evaluation using the node improved the CPU speed by 55 times in solving a minimum vertex cover problem, one of the NP-hard combinatorial optimization problems. Finally, we describe a cloud interface for the compute node to make the CMOS-APs more useful and to promote application development for it. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Combinatorial optimization / Annealing / Accelerator / Ising model |
| Paper # | SDM2019-36,ICD2019-1 |
| Date of Issue | 2019-07-31 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2019/8/7(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido Univ., Graduate School /Faculty of Information Science and |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Takahiro Shinada(Tohoku Univ.) / Makoto Nagata(Kobe Univ.) / 秋田 純一(金沢大)) |
| Vice Chair | Hiroshige Hirano(TowerJazz Panasonic) / Masafumi Takahashi(Toshiba-memory) / 廣瀬 裕(パナソニック) |
| Secretary | Hiroshige Hirano(Shizuoka Univ.) / Masafumi Takahashi(TOSHIBA MEMORY) / 廣瀬 裕(Tohoku Univ.) |
| Assistant | Takahiro Mori(AIST) / Nobuaki Kobayashi(Nihon Univ.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems |
| Sub Title (in English) | |
| Keyword(1) | Combinatorial optimization |
| Keyword(2) | Annealing |
| Keyword(3) | Accelerator |
| Keyword(4) | Ising model |
| 1st Author's Name | Masato Hayashi |
| 1st Author's Affiliation | Hitachi, Ltd.(Hitachi) |
| 2nd Author's Name | Takashi Takemoto |
| 2nd Author's Affiliation | Hitachi, Ltd.(Hitachi) |
| 3rd Author's Name | Chihiro Yoshimura |
| 3rd Author's Affiliation | Hitachi, Ltd.(Hitachi) |
| 4th Author's Name | Masanao Yamaoka |
| 4th Author's Affiliation | Hitachi, Ltd.(Hitachi) |
| Date | 2019-08-07 |
| Paper # | SDM2019-36,ICD2019-1 |
| Volume (vol) | vol.119 |
| Number (no) | SDM-161,ICD-162 |
| Page | pp.pp.1-5(SDM), pp.1-5(ICD), |
| #Pages | 5 |
| Date of Issue | 2019-07-31 (SDM, ICD) |