| Presentation | 2019-08-09 Evaluation of IC-Chip Noise Reduction using Magnetic Materials Kosuke Jike, Koh Watanabe, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata, Akihiro Takahashi, Yasunori Miyazawa, Masahiro Yamaguchi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Suppression of noise emitted from digital integrated circuit (IC) chip is expected by using magnetic materials. The frequency characteristics of noise shielding or even absorption of magnetic materials are to be properly tuned with the selection of their compositions. This reports investigate the effectiveness of noise suppression by measuring noises at on-chip and on-board locations. The prototype IC chips embed on-chip noise generator and noise monitoring circuitry and use the membrane of magnetic materials in assembly. On-chip voltage variation and on-board near magnetic fields are measured by on-chip voltage monitoring and magnetic probing techniques, in areas of IC chip and printed circuit board, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Noise emission / magnetic material / magnetic membrane / power noise / on-chip noise monitoring / near magnetic field measurements |
| Paper # | SDM2019-49,ICD2019-14 |
| Date of Issue | 2019-07-31 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2019/8/7(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido Univ., Graduate School /Faculty of Information Science and |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Takahiro Shinada(Tohoku Univ.) / Makoto Nagata(Kobe Univ.) / 秋田 純一(金沢大)) |
| Vice Chair | Hiroshige Hirano(TowerJazz Panasonic) / Masafumi Takahashi(Toshiba-memory) / 廣瀬 裕(パナソニック) |
| Secretary | Hiroshige Hirano(Shizuoka Univ.) / Masafumi Takahashi(TOSHIBA MEMORY) / 廣瀬 裕(Tohoku Univ.) |
| Assistant | Takahiro Mori(AIST) / Nobuaki Kobayashi(Nihon Univ.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of IC-Chip Noise Reduction using Magnetic Materials |
| Sub Title (in English) | |
| Keyword(1) | Noise emission |
| Keyword(2) | magnetic material |
| Keyword(3) | magnetic membrane |
| Keyword(4) | power noise |
| Keyword(5) | on-chip noise monitoring |
| Keyword(6) | near magnetic field measurements |
| 1st Author's Name | Kosuke Jike |
| 1st Author's Affiliation | Kobe University(Kobe Univ) |
| 2nd Author's Name | Koh Watanabe |
| 2nd Author's Affiliation | Kobe University(Kobe Univ) |
| 3rd Author's Name | Satoshi Tanaka |
| 3rd Author's Affiliation | Kobe University(Kobe Univ) |
| 4th Author's Name | Noriyuki Miura |
| 4th Author's Affiliation | Kobe University(Kobe Univ) |
| 5th Author's Name | Makoto Nagata |
| 5th Author's Affiliation | Kobe University(Kobe Univ) |
| 6th Author's Name | Akihiro Takahashi |
| 6th Author's Affiliation | Tohoku University(Tohoku Univ) |
| 7th Author's Name | Yasunori Miyazawa |
| 7th Author's Affiliation | Tohoku University(Tohoku Univ) |
| 8th Author's Name | Masahiro Yamaguchi |
| 8th Author's Affiliation | Tohoku University(Tohoku Univ) |
| Date | 2019-08-09 |
| Paper # | SDM2019-49,ICD2019-14 |
| Volume (vol) | vol.119 |
| Number (no) | SDM-161,ICD-162 |
| Page | pp.pp.79-83(SDM), pp.79-83(ICD), |
| #Pages | 5 |
| Date of Issue | 2019-07-31 (SDM, ICD) |