| Presentation | 2019-08-09 Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS “PN Body-Tied SOI-FET” Wataru Yabuki, Jiro Ida, Takayuki Mori, Koichiro Ishibashi, Yasuo Arai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study, We report the effect of the substrate bias (Vsub) and the positive charge (Qox) in the buried oxide (BOX) on super steep subthreshold slope (SS) “PN Body-Tied (PNBT) SOI-FET” proposed in our laboratory. The Qox in the BOX was evaluated with the specific test device. Removing the effect of the Qox and realizing the super steep SS, the necessity of Vsub, especially on P-channel, was systematically confirmed with measurements and simulations. It was founded out that the positive feedback by PNBT contributes to making the barrier height for reducing the leakage current and realizing the super steep SS, although the difference of the static barrier height is small only with Vsub and the Qox. We also propose modification on PNBT structure for realizing CMOS without Vsub bias. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SOI-FET / Steep Subthreshold Slope / Oxide Charge |
| Paper # | SDM2019-51,ICD2019-16 |
| Date of Issue | 2019-07-31 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2019/8/7(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido Univ., Graduate School /Faculty of Information Science and |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Takahiro Shinada(Tohoku Univ.) / Makoto Nagata(Kobe Univ.) / 秋田 純一(金沢大)) |
| Vice Chair | Hiroshige Hirano(TowerJazz Panasonic) / Masafumi Takahashi(Toshiba-memory) / 廣瀬 裕(パナソニック) |
| Secretary | Hiroshige Hirano(Shizuoka Univ.) / Masafumi Takahashi(TOSHIBA MEMORY) / 廣瀬 裕(Tohoku Univ.) |
| Assistant | Takahiro Mori(AIST) / Nobuaki Kobayashi(Nihon Univ.) / Tetsuya Hirose(Osaka Univ.) / Koji Nii(Floadia) / Takeshi Kuboki(Kyushu Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS “PN Body-Tied SOI-FET” |
| Sub Title (in English) | |
| Keyword(1) | SOI-FET |
| Keyword(2) | Steep Subthreshold Slope |
| Keyword(3) | Oxide Charge |
| 1st Author's Name | Wataru Yabuki |
| 1st Author's Affiliation | Kanazawa Institute of Technology(KIT) |
| 2nd Author's Name | Jiro Ida |
| 2nd Author's Affiliation | Kanazawa Institute of Technology(KIT) |
| 3rd Author's Name | Takayuki Mori |
| 3rd Author's Affiliation | Kanazawa Institute of Technology(KIT) |
| 4th Author's Name | Koichiro Ishibashi |
| 4th Author's Affiliation | University of Electro-Communications(UEC) |
| 5th Author's Name | Yasuo Arai |
| 5th Author's Affiliation | High Energy Accelerator Research Organization(KEK) |
| Date | 2019-08-09 |
| Paper # | SDM2019-51,ICD2019-16 |
| Volume (vol) | vol.119 |
| Number (no) | SDM-161,ICD-162 |
| Page | pp.pp.89-93(SDM), pp.89-93(ICD), |
| #Pages | 5 |
| Date of Issue | 2019-07-31 (SDM, ICD) |