Presentation 2019-07-31
Speedup of the Asynchronous Serial Multiplier by Concealing the Idle Phase for Digital Hearing Aids
Masahiro Nagata, Masafumi Kondo, Isao Kayono, Tomoyuki Yokogawa, Kazutami Arimoto, Yoichiro Sato,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Recently, digital hearing aids with DSP have spread through, but their battery life has remained for only a few days. For this problem, we applied an asynchronous circuit-based control method to a serial multiplier using only a single full adder (FA) and realized low power consumption and small area Multiply and ACcumulator (MAC). However, the calculation time increases due to the idle phase required for controlling asynchronous circuits, and it is difficult to obtain sufficient frequency characteristics when applied to filter circuits. Therefore, in this study, we propose a method of concealing the idle phase and reduce the calculation time by arranging an additional FA in parallel and complementarity controlling the two FAs. Then, we design the MAC based on the proposed method, confirm its operation by simulation and its effectiveness about power consumption.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Digital Hearing Aid / Dual-rail / Asynchronous Circuit / Serial Multiplier
Paper # CAS2019-22,VLD2019-28,SIP2019-38,MSS2019-22
Date of Issue 2019-07-23 (CAS, VLD, SIP, MSS)

Conference Information
Committee MSS / CAS / SIP / VLD
Conference Date 2019/7/30(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Iwate Univ.
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Shigemasa Takai(Osaka Univ.) / Taizo Yamawaki(Hitachi) / Naoyuki Aikawa(TUS) / Nozomu Togawa(Waseda Univ.)
Vice Chair Atsuo Ozaki(Osaka Inst. of Tech.) / Yasuhiro Takashima(Univ. of Kitakyushu) / Kazunori Hayashi(Osaka City Univ) / Yukihiro Bandou(NTT) / Daisuke Fukuda(Fujitsu Labs.)
Secretary Atsuo Ozaki(Osaka Univ.) / Yasuhiro Takashima(Hokkaido Univ.) / Kazunori Hayashi(Hitachi) / Yukihiro Bandou(Yamanashi Univ.) / Daisuke Fukuda(Hiroshima Univ.)
Assistant Naoki Hayashi(Osaka Univ.) / Hiroki Sato(Sony LSI Design) / Motoi Yamaguchi(Renesas Electronics) / / Kazuki Ikeda(Hitachi)

Paper Information
Registration To Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Speedup of the Asynchronous Serial Multiplier by Concealing the Idle Phase for Digital Hearing Aids
Sub Title (in English)
Keyword(1) Digital Hearing Aid
Keyword(2) Dual-rail
Keyword(3) Asynchronous Circuit
Keyword(4) Serial Multiplier
1st Author's Name Masahiro Nagata
1st Author's Affiliation Okayama Prefectural University(Okayama Prefectural Univ.)
2nd Author's Name Masafumi Kondo
2nd Author's Affiliation Kawasaki University of Medical Welfare(Kawasaki Univ. of Medical Welfare)
3rd Author's Name Isao Kayono
3rd Author's Affiliation Kawasaki University of Medical Welfare(Kawasaki Univ. of Medical Welfare)
4th Author's Name Tomoyuki Yokogawa
4th Author's Affiliation Okayama Prefectural University(Okayama Prefectural Univ.)
5th Author's Name Kazutami Arimoto
5th Author's Affiliation Okayama Prefectural University(Okayama Prefectural Univ.)
6th Author's Name Yoichiro Sato
6th Author's Affiliation Okayama Prefectural University(Okayama Prefectural Univ.)
Date 2019-07-31
Paper # CAS2019-22,VLD2019-28,SIP2019-38,MSS2019-22
Volume (vol) vol.119
Number (no) CAS-153,VLD-154,SIP-155,MSS-156
Page pp.pp.99-104(CAS), pp.99-104(VLD), pp.99-104(SIP), pp.99-104(MSS),
#Pages 6
Date of Issue 2019-07-23 (CAS, VLD, SIP, MSS)