| Presentation | 2019-07-24 Proposal of Scalable Vector Instruction Set for Embedded RISC-V Processor Yoshiki Kimura, Tomoya Kikuchi, Kanemitsu Ootsu, Takashi Yokota, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, the use of FPGA in the embedded field has increased. However, development using FPGA is high development costs. Therefore, the development cost can be reduced by combining the dedicated circuit and the soft-core processor. If the performance of the soft-core processor improves, the development cost can be suppressed. Recently, even in the embedded field, opportunities for processing with data parallelism such as image processing are increasing. SIMD parallel processing is effective for speeding up processing with data parallelism. In the conventional SIMD instruction, the operation performance can be changed by changing the number of concurrent operations, but it is necessary to remake the machine language code. On the other hand, RISC-V is an open ISA, and its use in the embedded field is expected to increase. Therefore, SIMD parallel processing is also important in RISC-V. In this paper, we propose a scalable vector instruction set in which machine language code for RISC-V does not depend on the number of operation units, and describe a development method of vector processing software. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RISC-V / vector processing / soft-core processor |
| Paper # | CPSY2019-18,DC2019-18 |
| Date of Issue | 2019-07-17 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2019/7/24(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitami Civic Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing Systems and Dependable Computing |
| Chair | Hidetsugu Irie(Univ. of Tokyo) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) / Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Michihiro Koibuchi(Nagoya Inst. of Tech.) / Kota Nakajima(Hokkaido Univ.) / Hiroshi Takahashi(Nihon Univ.) / (Chiba Univ.) |
| Assistant | Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal of Scalable Vector Instruction Set for Embedded RISC-V Processor |
| Sub Title (in English) | |
| Keyword(1) | RISC-V |
| Keyword(2) | vector processing |
| Keyword(3) | soft-core processor |
| 1st Author's Name | Yoshiki Kimura |
| 1st Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| 2nd Author's Name | Tomoya Kikuchi |
| 2nd Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| 3rd Author's Name | Kanemitsu Ootsu |
| 3rd Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| 4th Author's Name | Takashi Yokota |
| 4th Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| Date | 2019-07-24 |
| Paper # | CPSY2019-18,DC2019-18 |
| Volume (vol) | vol.119 |
| Number (no) | CPSY-147,DC-148 |
| Page | pp.pp.21-26(CPSY), pp.21-26(DC), |
| #Pages | 6 |
| Date of Issue | 2019-07-17 (CPSY, DC) |