Presentation | 2019-07-23 Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed hardware implementation is an important issue. We implemented on the SAKURA-X board the main part extracted from the fastest FPGA implementation that calculates the optimal Ate pairing on a BN curve using a pipelined modular multiplier. We performed side-channel attack experiments on this implementation and discussed side-channel security of the original pairing implementation. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Bilinear pairing / advanced cryptography / optimal Ate pairing / pipelined modular multiplier / FPGA pairing implementation / side-channel attack / side-channel security |
Paper # | ISEC2019-29,SITE2019-23,BioX2019-21,HWS2019-24,ICSS2019-27,EMM2019-32 |
Date of Issue | 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |
Conference Information | |
Committee | ISEC / SITE / ICSS / EMM / HWS / BioX / IPSJ-CSEC / IPSJ-SPT |
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Conference Date | 2019/7/23(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Kochi University of Technology |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Security, etc. |
Chair | Shiho Moriai(NICT) / Tetsuya Morizumi(Kanagawa Univ.) / Hiroki Takakura(NII) / Masaki Kawamura(Yamaguchi Univ.) / Shinichi Kawamura(Toshiba) / Akira Otsuka(IISEC) |
Vice Chair | Shoichi Hirose(Univ. of Fukui) / Tetsuya Izu(Fujitsu Labs.) / Masaru Ogawa(Kobe Gakuin Univ.) / Takushi Otani(Kibi International Univ.) / Katsunari Yoshioka(Yokohama National Univ.) / Kazunori Kamiya(NTT) / Motoi Iwata(Osaka Prefecture Univ.) / Tetsuya Kojima(NIT,Tokyo College) / Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Tetsushi Ohki(Shizuoka Univ.) / Takahiro Aoki(Fujitsu Labs.) |
Secretary | Shoichi Hirose(NICT) / Tetsuya Izu(Tsukuba Univ.) / Masaru Ogawa(Toyo Eiwa Univ.) / Takushi Otani(KDDI Research) / Katsunari Yoshioka(NICT) / Kazunori Kamiya(KDDI labs.) / Motoi Iwata(NIT, Nagano College) / Tetsuya Kojima(Nagase) / Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Tetsushi Ohki(Univ. of Electro-Comm.) / Takahiro Aoki(SECOM) |
Assistant | Dai Yamamoto(Fujitsu Labs.) / Yuuji Suga(IIJ) / Nobuyuki Yoshinaga(Yamaguchi Pref Univ.) / Daisuke Suzuki(Hokuriku Univ.) / Keisuke Kito(Mitsubishi Electric) / Toshihiro Yamauchi(Okayama Univ.) / Masaki Inamura(Tokyo Denki Univ.) / Kazuhiro Kono(Kansai Univ.) / / Daishi Watabe(Saitama Inst. of Tech.) / Ryota Horie(Shibaura Inst. of Tech.) |
Paper Information | |
Registration To | Technical Committee on Information Security / Technical Committee on Social Implications of Technology and Information Ethics / Technical Committee on Information and Communication System Security / Technical Committee on Enriched MultiMedia / Technical Committee on Hardware Security / Technical Committee on Biometrics / Special Interest Group on Computer Security / Special Interest Group on Security Psychology and Trust |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier |
Sub Title (in English) | |
Keyword(1) | Bilinear pairing |
Keyword(2) | advanced cryptography |
Keyword(3) | optimal Ate pairing |
Keyword(4) | pipelined modular multiplier |
Keyword(5) | FPGA pairing implementation |
Keyword(6) | side-channel attack |
Keyword(7) | side-channel security |
1st Author's Name | Mitsufumi Yamazaki |
1st Author's Affiliation | Yokohama National University(YNU) |
2nd Author's Name | Junichi Sakamoto |
2nd Author's Affiliation | Yokohama National University(YNU) |
3rd Author's Name | Yuta Okuaki |
3rd Author's Affiliation | Yokohama National University(YNU) |
4th Author's Name | Tsutomu Matsumoto |
4th Author's Affiliation | Yokohama National University(YNU) |
Date | 2019-07-23 |
Paper # | ISEC2019-29,SITE2019-23,BioX2019-21,HWS2019-24,ICSS2019-27,EMM2019-32 |
Volume (vol) | vol.119 |
Number (no) | ISEC-140,SITE-141,BioX-142,HWS-143,ICSS-144,EMM-145 |
Page | pp.pp.151-156(ISEC), pp.151-156(SITE), pp.151-156(BioX), pp.151-156(HWS), pp.151-156(ICSS), pp.151-156(EMM), |
#Pages | 6 |
Date of Issue | 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |