| Presentation | 2019-07-23 Side-channel leakage evaluation of cryptographic module by IC chip level consumption simulation Kazuki Yasuda, Kazuki Monta, Akihiro Tsukioka, Noriyuki Miura, Makoto Nagata, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the development of the information society, side-channel information leakage due to power supply noise in a cryptographic module using semiconductor integrated circuit (IC chip) technology has become an issue. In this research, we propose a method to make chip level simulation efficient by using a transistor device model for power consumption current of a cryptographic engine mounted on an IC chip. The chip to be evaluated is equipped with the Advanced Encryption Standard (AES) encryption. There are two target files. One is a netlist in which logic operation called RTL is described from combination of transfer between register and logic operation and logic synthesis is performed, and the other is netlist in which placement and routing are performed using logic synthesized netlist. We operated simulation during cryptographic and obtained the waveform of the wire consumption current. We operate CPA using the acquired waveform data, and power supply noise evaluation was performed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | IC chip / Power Noise / Crypto Modules / Side-channel leakage / AES / simulation |
| Paper # | ISEC2019-27,SITE2019-21,BioX2019-19,HWS2019-22,ICSS2019-25,EMM2019-30 |
| Date of Issue | 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |
| Conference Information | |
| Committee | ISEC / SITE / ICSS / EMM / HWS / BioX / IPSJ-CSEC / IPSJ-SPT |
|---|---|
| Conference Date | 2019/7/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi University of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Security, etc. |
| Chair | Shiho Moriai(NICT) / Tetsuya Morizumi(Kanagawa Univ.) / Hiroki Takakura(NII) / Masaki Kawamura(Yamaguchi Univ.) / Shinichi Kawamura(Toshiba) / Akira Otsuka(IISEC) |
| Vice Chair | Shoichi Hirose(Univ. of Fukui) / Tetsuya Izu(Fujitsu Labs.) / Masaru Ogawa(Kobe Gakuin Univ.) / Takushi Otani(Kibi International Univ.) / Katsunari Yoshioka(Yokohama National Univ.) / Kazunori Kamiya(NTT) / Motoi Iwata(Osaka Prefecture Univ.) / Tetsuya Kojima(NIT,Tokyo College) / Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Tetsushi Ohki(Shizuoka Univ.) / Takahiro Aoki(Fujitsu Labs.) |
| Secretary | Shoichi Hirose(NICT) / Tetsuya Izu(Tsukuba Univ.) / Masaru Ogawa(Toyo Eiwa Univ.) / Takushi Otani(KDDI Research) / Katsunari Yoshioka(NICT) / Kazunori Kamiya(KDDI labs.) / Motoi Iwata(NIT, Nagano College) / Tetsuya Kojima(Nagase) / Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Tetsushi Ohki(Univ. of Electro-Comm.) / Takahiro Aoki(SECOM) |
| Assistant | Dai Yamamoto(Fujitsu Labs.) / Yuuji Suga(IIJ) / Nobuyuki Yoshinaga(Yamaguchi Pref Univ.) / Daisuke Suzuki(Hokuriku Univ.) / Keisuke Kito(Mitsubishi Electric) / Toshihiro Yamauchi(Okayama Univ.) / Masaki Inamura(Tokyo Denki Univ.) / Kazuhiro Kono(Kansai Univ.) / / Daishi Watabe(Saitama Inst. of Tech.) / Ryota Horie(Shibaura Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Information Security / Technical Committee on Social Implications of Technology and Information Ethics / Technical Committee on Information and Communication System Security / Technical Committee on Enriched MultiMedia / Technical Committee on Hardware Security / Technical Committee on Biometrics / Special Interest Group on Computer Security / Special Interest Group on Security Psychology and Trust |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Side-channel leakage evaluation of cryptographic module by IC chip level consumption simulation |
| Sub Title (in English) | |
| Keyword(1) | IC chip |
| Keyword(2) | Power Noise |
| Keyword(3) | Crypto Modules |
| Keyword(4) | Side-channel leakage |
| Keyword(5) | AES |
| Keyword(6) | simulation |
| 1st Author's Name | Kazuki Yasuda |
| 1st Author's Affiliation | Kobe University(Kobe Univ.) |
| 2nd Author's Name | Kazuki Monta |
| 2nd Author's Affiliation | Kobe University(Kobe Univ.) |
| 3rd Author's Name | Akihiro Tsukioka |
| 3rd Author's Affiliation | Kobe University(Kobe Univ.) |
| 4th Author's Name | Noriyuki Miura |
| 4th Author's Affiliation | Kobe University(Kobe Univ.) |
| 5th Author's Name | Makoto Nagata |
| 5th Author's Affiliation | Kobe University(Kobe Univ.) |
| Date | 2019-07-23 |
| Paper # | ISEC2019-27,SITE2019-21,BioX2019-19,HWS2019-22,ICSS2019-25,EMM2019-30 |
| Volume (vol) | vol.119 |
| Number (no) | ISEC-140,SITE-141,BioX-142,HWS-143,ICSS-144,EMM-145 |
| Page | pp.pp.139-143(ISEC), pp.139-143(SITE), pp.139-143(BioX), pp.139-143(HWS), pp.139-143(ICSS), pp.139-143(EMM), |
| #Pages | 5 |
| Date of Issue | 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |