| Presentation | 2019-07-23 A Formal Approach to Verifying Trojan-freeness of Cryptographic Circuits Based on Galois-Field Arithmetic Akira Ito, Rei Ueno, Naofumi Homma, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a formal method for verifying whether Hardware Trojan (HT) exists or not (i.e., HT-freeness) in cryptographic hardware. The proposed method focuses on GF arithmetic circuits which are commonly used for a major part of modern cryptographic hardware. Since the functionality of GF arithmetic circuits can be given by a set of GF equations, the proposed method detects the existence of HTs or verifies HT-freeness by checking the equivalence between GF equations (i.e., circuit specification) and flattened gate-level netlist of a target circuit. In the proposed method, we first derive GF equations (i.e., circuit specification) over a representation of Boolean polynomial ring using the zero-suppressed binary decision diagram (ZDD). We then construct the ZDD representation of the target netlist, and finally check whether or not the two ZDDs are isomorphic, which make it possible to perform an efficient and complete HT-freeness verification. In this paper, we demonstrate the highest efficiency of the proposed method through the experimental verification of GF multipliers with various input length including practical ones used in elliptic curve cryptography, and 128-bit AES hardware datapath. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware Trojan detection / Galois-field circuits / Formal verification |
| Paper # | ISEC2019-26,SITE2019-20,BioX2019-18,HWS2019-21,ICSS2019-24,EMM2019-29 |
| Date of Issue | 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |
| Conference Information | |
| Committee | ISEC / SITE / ICSS / EMM / HWS / BioX / IPSJ-CSEC / IPSJ-SPT |
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| Conference Date | 2019/7/23(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi University of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Security, etc. |
| Chair | Shiho Moriai(NICT) / Tetsuya Morizumi(Kanagawa Univ.) / Hiroki Takakura(NII) / Masaki Kawamura(Yamaguchi Univ.) / Shinichi Kawamura(Toshiba) / Akira Otsuka(IISEC) |
| Vice Chair | Shoichi Hirose(Univ. of Fukui) / Tetsuya Izu(Fujitsu Labs.) / Masaru Ogawa(Kobe Gakuin Univ.) / Takushi Otani(Kibi International Univ.) / Katsunari Yoshioka(Yokohama National Univ.) / Kazunori Kamiya(NTT) / Motoi Iwata(Osaka Prefecture Univ.) / Tetsuya Kojima(NIT,Tokyo College) / Makoto Ikeda(Univ. of Tokyo) / Yasuhisa Shimazaki(Renesas Electronics) / Tetsushi Ohki(Shizuoka Univ.) / Takahiro Aoki(Fujitsu Labs.) |
| Secretary | Shoichi Hirose(NICT) / Tetsuya Izu(Tsukuba Univ.) / Masaru Ogawa(Toyo Eiwa Univ.) / Takushi Otani(KDDI Research) / Katsunari Yoshioka(NICT) / Kazunori Kamiya(KDDI labs.) / Motoi Iwata(NIT, Nagano College) / Tetsuya Kojima(Nagase) / Makoto Ikeda(SECOM) / Yasuhisa Shimazaki(Kyushu Univ.) / Tetsushi Ohki(Univ. of Electro-Comm.) / Takahiro Aoki(SECOM) |
| Assistant | Dai Yamamoto(Fujitsu Labs.) / Yuuji Suga(IIJ) / Nobuyuki Yoshinaga(Yamaguchi Pref Univ.) / Daisuke Suzuki(Hokuriku Univ.) / Keisuke Kito(Mitsubishi Electric) / Toshihiro Yamauchi(Okayama Univ.) / Masaki Inamura(Tokyo Denki Univ.) / Kazuhiro Kono(Kansai Univ.) / / Daishi Watabe(Saitama Inst. of Tech.) / Ryota Horie(Shibaura Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Information Security / Technical Committee on Social Implications of Technology and Information Ethics / Technical Committee on Information and Communication System Security / Technical Committee on Enriched MultiMedia / Technical Committee on Hardware Security / Technical Committee on Biometrics / Special Interest Group on Computer Security / Special Interest Group on Security Psychology and Trust |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Formal Approach to Verifying Trojan-freeness of Cryptographic Circuits Based on Galois-Field Arithmetic |
| Sub Title (in English) | |
| Keyword(1) | Hardware Trojan detection |
| Keyword(2) | Galois-field circuits |
| Keyword(3) | Formal verification |
| 1st Author's Name | Akira Ito |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Rei Ueno |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Naofumi Homma |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2019-07-23 |
| Paper # | ISEC2019-26,SITE2019-20,BioX2019-18,HWS2019-21,ICSS2019-24,EMM2019-29 |
| Volume (vol) | vol.119 |
| Number (no) | ISEC-140,SITE-141,BioX-142,HWS-143,ICSS-144,EMM-145 |
| Page | pp.pp.133-138(ISEC), pp.133-138(SITE), pp.133-138(BioX), pp.133-138(HWS), pp.133-138(ICSS), pp.133-138(EMM), |
| #Pages | 6 |
| Date of Issue | 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |