| Presentation | 2019-06-12 Architectural Support in CGLA for Quick Compilation and Fine Tuning Yasuhiko Nakashima, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | At present, the benefits of power reduction and cost reduction due to the miniaturization of semiconductors are lost, and the coarse grained reconfigurable array (CGRA) is being used as one of the platforms to complement the Neumann type platforms. However, it is important to shorten the Turn Around Time (TAT) of searching algorithms and tuning of performance. In FPGAs, which are fine-grained reconfigurable devices, it is not uncommon for synthetic placement and routing of large-scale circuits to take several hours, whereas the compilation time of CGRA, which is a fine-grained reconfigurable device, should be short. However, if computational resources and freedom of reconstruction are limited, exploratory compilation is required, and in large-scale CGRA, exponential compilation time becomes the bottleneck for programming. In this paper, the linear array CGRA (CGLA), which does not require exploratory compilation but is concerned about the increase in the number of required registers, is taken up, and the number of registers required for application mapping is evaluated. If there are 16 propagation registers in each stage, various applications can be mapped, and the propagation register utilization of one stage per application can be up to 100% [16] to 44% [7] (overall average 70% [11.2]. It is found that waste is small. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | GRA / compiler |
| Paper # | CPSY2019-9,DC2019-9 |
| Date of Issue | 2019-06-04 (CPSY, DC) |
| Conference Information | |
| Committee | DC / CPSY / IPSJ-ARC |
|---|---|
| Conference Date | 2019/6/11(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | National Park Resort Ibusuki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Architecture, Computer Systems, Dependable Computing, etc. (HotSPA2019) |
| Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Hiroshi Inoue(Kyushu Univ.) |
| Vice Chair | Hiroshi Takahashi(Ehime Univ.) / Michihiro Koibuchi(NII) / Kota Nakajima(Fujitsu Lab.) |
| Secretary | Hiroshi Takahashi(Nihon Univ.) / Michihiro Koibuchi(Chiba Univ.) / Kota Nakajima(Nagoya Inst. of Tech.) / (Hokkaido Univ.) |
| Assistant | / Eiji Arima(Univ. of Tokyo) / Shugo Ogawa(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Architectural Support in CGLA for Quick Compilation and Fine Tuning |
| Sub Title (in English) | |
| Keyword(1) | GRA |
| Keyword(2) | compiler |
| 1st Author's Name | Yasuhiko Nakashima |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2019-06-12 |
| Paper # | CPSY2019-9,DC2019-9 |
| Volume (vol) | vol.119 |
| Number (no) | CPSY-76,DC-77 |
| Page | pp.pp.71-76(CPSY), pp.71-76(DC), |
| #Pages | 6 |
| Date of Issue | 2019-06-04 (CPSY, DC) |