| Presentation | 2019-05-15 The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process Hideharu Amano, Hideto Kayashima, Tsunaaki Shidei, Takuya Kojima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | VLD2019-5 |
| Date of Issue | 2019-05-08 (VLD) |
| Conference Information | |
| Committee | VLD / IPSJ-SLDM |
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| Conference Date | 2019/5/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ookayama Campus, Tokyo Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Chair | Noriyuki Minegishi(Mitsubishi Electric) / Yutaka Tamiya(Fujitsu Lab.) |
| Vice Chair | Nozomu Togawa(Waseda Univ.) |
| Secretary | Nozomu Togawa(NTT) / (Univ. of Aizu) |
| Assistant | / Hiroe Iwasaki(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process |
| Sub Title (in English) | |
| Keyword(1) | |
| Keyword(2) | |
| Keyword(3) | |
| 1st Author's Name | Hideharu Amano |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Hideto Kayashima |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| 3rd Author's Name | Tsunaaki Shidei |
| 3rd Author's Affiliation | Keio University(Keio Univ.) |
| 4th Author's Name | Takuya Kojima |
| 4th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2019-05-15 |
| Paper # | VLD2019-5 |
| Volume (vol) | vol.119 |
| Number (no) | VLD-25 |
| Page | pp.pp.31-36(VLD), |
| #Pages | 6 |
| Date of Issue | 2019-05-08 (VLD) |