Presentation 2019-05-15
SRAM-Based Synthesis for Multi-Output Gates
Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation with SRAM for multiple-output gates. Due to SRAM's multi-output nature and SRAM cell's compact structure, using multi-output gates to represent the circuit may become good for area efficiency if synthesized in an ideal way. We will compare the traditional implementation and SRAM-based implementation of look-up tables(LUTs) by modeling, and perform the synthesis by merging the nodes with several methods. Finally, we estimate the possibility of area reduction based on the experimental results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) multi-output gateSRAMLUTlogic synthesis
Paper # VLD2019-4
Date of Issue 2019-05-08 (VLD)

Conference Information
Committee VLD / IPSJ-SLDM
Conference Date 2019/5/15(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Ookayama Campus, Tokyo Institute of Technology
Topics (in Japanese) (See Japanese page)
Topics (in English) System Design, etc.
Chair Noriyuki Minegishi(Mitsubishi Electric) / Yutaka Tamiya(Fujitsu Lab.)
Vice Chair Nozomu Togawa(Waseda Univ.)
Secretary Nozomu Togawa(NTT) / (Univ. of Aizu)
Assistant / Hiroe Iwasaki(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) SRAM-Based Synthesis for Multi-Output Gates
Sub Title (in English)
Keyword(1) multi-output gateSRAMLUTlogic synthesis
1st Author's Name Xingming Le
1st Author's Affiliation The University of Tokyo(The Univ. of Tokyo)
2nd Author's Name Amir Masoud Gharehbaghi
2nd Author's Affiliation The University of Tokyo(The Univ. of Tokyo)
3rd Author's Name Masahiro Fujita
3rd Author's Affiliation The University of Tokyo(The Univ. of Tokyo)
Date 2019-05-15
Paper # VLD2019-4
Volume (vol) vol.119
Number (no) VLD-25
Page pp.pp.25-30(VLD),
#Pages 6
Date of Issue 2019-05-08 (VLD)