Presentation | 2019-05-16 A Design of Peak Current Detector Considering Processing and Wiring Delay Yudai Furukawa, Kazuya Uetsuhara, Yuichiro Shibata, Tadashi Suetsugu, Fujio Kurokawa, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The current mode control is used to realize high stability and quick response as the control method for dc-dc converters. Especially, the peak current mode control performs such properties. In the digital control switching power supply, it is important to implement the peak current mode control reducing a bad influence of delay time included in the controller. The purpose of this paper is to discuss the design of peak current mode control with current ? frequency conversion considering the processing and wiring delay, which is the cause of an incorrect action, in the Field Programmable Gate Array (FPGA). As a result, it is revealed that the timing adjustment of processed signals in FPGA brings a proper operation. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Peak Current Mode Control / Current to Frequency Conversion |
Paper # | EE2019-4 |
Date of Issue | 2019-05-09 (EE) |
Conference Information | |
Committee | EE / IEE-HCA |
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Conference Date | 2019/5/16(2days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Switching power supply, New industrial and home appliance for power, others |
Chair | Tadatoshi Babasaki(NTT Facilities) |
Vice Chair | Keiichi Hirose(NTT Facilities) / Tadashi Suetsugu(Fukuoka Univ.) |
Secretary | Keiichi Hirose(Sojo Univ.) / Tadashi Suetsugu(Nagasaki Inst. of Applied Science) |
Assistant | Takashi Matsushita(NTT-F) / Tetsuya Oshikata(ShinDengen) / Yuu Yonezawa(Fujitsu Lab.) |
Paper Information | |
Registration To | Technical Committee on Energy Engineering in Electronics and Communications / Technical Meeting on Home and Consumer Appliances |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Design of Peak Current Detector Considering Processing and Wiring Delay |
Sub Title (in English) | |
Keyword(1) | Peak Current Mode Control |
Keyword(2) | Current to Frequency Conversion |
1st Author's Name | Yudai Furukawa |
1st Author's Affiliation | Fukuoka University(Fukuoka Univ.) |
2nd Author's Name | Kazuya Uetsuhara |
2nd Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
3rd Author's Name | Yuichiro Shibata |
3rd Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
4th Author's Name | Tadashi Suetsugu |
4th Author's Affiliation | Fukuoka University(Fukuoka Univ.) |
5th Author's Name | Fujio Kurokawa |
5th Author's Affiliation | Nagasaki Insutitute of Applied Science(NiAS) |
Date | 2019-05-16 |
Paper # | EE2019-4 |
Volume (vol) | vol.119 |
Number (no) | EE-32 |
Page | pp.pp.17-21(EE), |
#Pages | 5 |
Date of Issue | 2019-05-09 (EE) |