| Presentation | 2019-05-10 An FPGA Implementation of the Semantic Segmentation Model with Multi-path Structure Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since the convolutional neural network has a high-performance recognition accuracy, it is expected to implement various applications on an embedded vision system. An FPGA can calculate the inference algorithm with low-latency and low power consumption using a specific circuit. In the paper, we propose a quantized weights with weight pruning, to reduce the operation cost and parameters of PSPNet. We set 8-bit precision for CNN weights and activations using a linear quantization to reduce circuit area. And we prune wasteful weights to reduce MACs and weights parameters. We apply an indirect memory access architecture to skip zero part and propose the weight parallel 2D convolutional circuit. It can be applied to the AlexNet based CNN, which has different size kernels. Thus, we design the AlexNet based PSPNet to reduce the number of layers toward low-latency computation. In the experiment, by applying the proposed scheme, it reduces the 93% of weight parameter. We implement the proposed PSPNet on a Xilinx zcu102 evaluation board, by using Xilinx SDSoC 2018.2.2. It archived 79.0 frames per second (FPS) on self-driving dataset. Compared with single path CNN, it was 14.0% times higher accuracy. In terms of its over-head of the hardware area, it requires 1.08 times BRAMs, 1.38 times DSPs, 2.30 times FFs and 1.67 times LUTs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Convolutional Neural Network / FPGA / Semantic Segmentation / Quantization / Pruning |
| Paper # | RECONF2019-10 |
| Date of Issue | 2019-05-02 (RECONF) |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2019/5/9(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tokyo Tech Front |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Chair | Masato Motomura(Tokyo Tech.) |
| Vice Chair | Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) |
| Secretary | Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation of the Semantic Segmentation Model with Multi-path Structure |
| Sub Title (in English) | |
| Keyword(1) | Convolutional Neural Network |
| Keyword(2) | FPGA |
| Keyword(3) | Semantic Segmentation |
| Keyword(4) | Quantization |
| Keyword(5) | Pruning |
| 1st Author's Name | Youki Sada |
| 1st Author's Affiliation | Tokyo Institute of Technology(titech) |
| 2nd Author's Name | Masayuki Shimoda |
| 2nd Author's Affiliation | Tokyo Institute of Technology(titech) |
| 3rd Author's Name | Shimpei Sato |
| 3rd Author's Affiliation | Tokyo Institute of Technology(titech) |
| 4th Author's Name | Hiroki Nakahara |
| 4th Author's Affiliation | Tokyo Institute of Technology(titech) |
| Date | 2019-05-10 |
| Paper # | RECONF2019-10 |
| Volume (vol) | vol.119 |
| Number (no) | RECONF-18 |
| Page | pp.pp.49-54(RECONF), |
| #Pages | 6 |
| Date of Issue | 2019-05-02 (RECONF) |