Presentation 2019-05-15
Approximate Computing Technique Using Memoization and Simplified Multiplication
Yoshinori Ono, Kimiyoshi Usami,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In embedded systems, approximate computing can strongly promote reduction of execution time and energy consumption in exchange for some output errors. We focused on “Fuzzy memoization”, which is one of the approximate computing techniques. We improved it by using simplifying multiplication. By this improvement, we have developed a novel technique to reduce execution time and energy consumption while keeping output precision. Then, we implemented an application for grayscale filters on the Zynq system that contains ARM-based processor and field-programmable gate array (FPGA). As a result, this system could reduce the execution time by up to 28% and reduce the energy consumption by 11% in spite of very high-quality output images.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Approximate Computing / Image Processing / Field Programmable Gate Array (FPGA)
Paper # VLD2019-2
Date of Issue 2019-05-08 (VLD)

Conference Information
Committee VLD / IPSJ-SLDM
Conference Date 2019/5/15(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Ookayama Campus, Tokyo Institute of Technology
Topics (in Japanese) (See Japanese page)
Topics (in English) System Design, etc.
Chair Noriyuki Minegishi(Mitsubishi Electric) / Yutaka Tamiya(Fujitsu Lab.)
Vice Chair Nozomu Togawa(Waseda Univ.)
Secretary Nozomu Togawa(NTT) / (Univ. of Aizu)
Assistant / Hiroe Iwasaki(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Approximate Computing Technique Using Memoization and Simplified Multiplication
Sub Title (in English)
Keyword(1) Approximate Computing
Keyword(2) Image Processing
Keyword(3) Field Programmable Gate Array (FPGA)
1st Author's Name Yoshinori Ono
1st Author's Affiliation Shibaura Institute of Technology(SIT)
2nd Author's Name Kimiyoshi Usami
2nd Author's Affiliation Shibaura Institute of Technology(SIT)
Date 2019-05-15
Paper # VLD2019-2
Volume (vol) vol.119
Number (no) VLD-25
Page pp.pp.13-18(VLD),
#Pages 6
Date of Issue 2019-05-08 (VLD)