| Presentation | 2019-05-09 Efficient Instruction Fetch Architectures for a RISC-V Soft Processor Hiromu Miyazaki, Junya Miura, Kenji Kise, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We aim to develop a cost-effective RISC-V scalar processor of pipelining for FPGAs. In this report, we try to implement an efficient instruction fetch unit. We clarify the problem of an instruction fetch unit in the processor that support the RISC-V compressed instructions. To solve the problem, we propose two instruction fetch units. We implement the proposed fetch units and evaluate their performance, hardware resources, and operating frequency. Through the evaluation, we show that the proposed unit with a compressed cache is the best and achieves 21.8% better fetch performance than a baseline architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft Processor / RISC-V / FPGA / Instruction Fetch / Instruction Cache / Compressed Instruction |
| Paper # | RECONF2019-1 |
| Date of Issue | 2019-05-02 (RECONF) |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2019/5/9(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tokyo Tech Front |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Chair | Masato Motomura(Tokyo Tech.) |
| Vice Chair | Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) |
| Secretary | Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Efficient Instruction Fetch Architectures for a RISC-V Soft Processor |
| Sub Title (in English) | |
| Keyword(1) | Soft Processor |
| Keyword(2) | RISC-V |
| Keyword(3) | FPGA |
| Keyword(4) | Instruction Fetch |
| Keyword(5) | Instruction Cache |
| Keyword(6) | Compressed Instruction |
| 1st Author's Name | Hiromu Miyazaki |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Junya Miura |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Kenji Kise |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2019-05-09 |
| Paper # | RECONF2019-1 |
| Volume (vol) | vol.119 |
| Number (no) | RECONF-18 |
| Page | pp.pp.1-6(RECONF), |
| #Pages | 6 |
| Date of Issue | 2019-05-02 (RECONF) |