| Presentation | 2019-04-19 Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | SFQ/CMOS hybrid system, which is a hybridized system of SFQ circuits and CMOS memories, has been proposed as a large-scale memory solution for single-flux-quantum (SFQ) circuits. In this study, we designed and tested an SFQ microprocessor with an SFQ/CMOS hybrid memory, which we had implemented so far, for the demonstration of the SFQ/CMOS hybrid system. We adopted a one-instruction-set-computer architecture, SUBNEG. The system was designed and implemented with superconducting interface circuits by using the Josephson integrated circuit process, AIST-ADP2. A 64-kb SFQ/CMOS hybrid memory was combined with the SFQ microprocessor, where SFQ processor can access to a 16×4-bit memory space. In the measurement, the correct operation between the SFQ processor and the CMOS memory was obtained, and a simple integer sorting program was demonstrated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ/CMOS hybrid system / Josephson/CMOS hybrid memory / SFQ circuits / SRAM / one-instruction-set computer |
| Paper # | SCE2019-2 |
| Date of Issue | 2019-04-12 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2019/4/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroaki Myoren(Saitama Univ.) |
| Vice Chair | |
| Secretary | (Nagoya Univ.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor |
| Sub Title (in English) | |
| Keyword(1) | SFQ/CMOS hybrid system |
| Keyword(2) | Josephson/CMOS hybrid memory |
| Keyword(3) | SFQ circuits |
| Keyword(4) | SRAM |
| Keyword(5) | one-instruction-set computer |
| 1st Author's Name | Yuki Hironaka |
| 1st Author's Affiliation | Yokohama National University(Yokohama National Univ.) |
| 2nd Author's Name | Yuki Yamanashi |
| 2nd Author's Affiliation | Yokohama National University(Yokohama National Univ.) |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Yokohama National University(Yokohama National Univ.) |
| Date | 2019-04-19 |
| Paper # | SCE2019-2 |
| Volume (vol) | vol.119 |
| Number (no) | SCE-10 |
| Page | pp.pp.7-11(SCE), |
| #Pages | 5 |
| Date of Issue | 2019-04-12 (SCE) |