| Presentation | 2019-04-19 Design and demonstration of an adiabatic-quantum-flux-parametron field-programmable gate array using Josephson-CMOS hybrid memories Yukihiro Okuma, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is considerably reduced thanks to the adiabatic switching of the junctions. The lack of high-density memories in the AQFP logic, however, makes it challenging to realize large-scale information processing systems with the use of pure AQFP circuits. We have been developing a Josephson-CMOS hybrid memory to overcome the memory bottleneck in AQFP digital systems. By utilizing the high sensitivity of the AQFP gate, the output current from CMOS memories can be significantly decreased resulting in the reduction of the power consumption. In this study, we designed and fabricated a low-power area-efficient AQFP-CMOS hybrid field-programmable gate array (FPGA), where a CMOS memory is utilized as a rewritable read-only memory to control the AQFP circuits. The AQFP circuit for the AQFP-CMOS hybrid FPGA is composed of logic blocks, switch blocks and connection blocks, which are clocked by four-phase excitation currents. The AQFP-CMOS hybrid FPGA is fabricated by using the AIST 10 kA/cm2 Nb high-speed standard process and the Rhom 0.18 μm CMOS process. The area and power consumption of the two-by-two logic-cell system are estimated to be about 6.56 mm2 and 12.4 nW at 5 GHz operations, respectively. We demonstrated the operation of the AQFP-CMOS hybrid FPGA at low speed by combining the AQFP logic and the CMOS memory. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | AQFP / FPGA / Josephson-CMOS hybrid memory / superconducting integrated circuit / QFP |
| Paper # | SCE2019-1 |
| Date of Issue | 2019-04-12 (SCE) |
| Conference Information | |
| Committee | SCE |
|---|---|
| Conference Date | 2019/4/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroaki Myoren(Saitama Univ.) |
| Vice Chair | |
| Secretary | (Nagoya Univ.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and demonstration of an adiabatic-quantum-flux-parametron field-programmable gate array using Josephson-CMOS hybrid memories |
| Sub Title (in English) | |
| Keyword(1) | AQFP |
| Keyword(2) | FPGA |
| Keyword(3) | Josephson-CMOS hybrid memory |
| Keyword(4) | superconducting integrated circuit |
| Keyword(5) | QFP |
| 1st Author's Name | Yukihiro Okuma |
| 1st Author's Affiliation | Yokohama National University(Yokohama Nat. Univ.) |
| 2nd Author's Name | Naoki Takeuchi |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Nat. Univ.) |
| 3rd Author's Name | Yuki Yamanashi |
| 3rd Author's Affiliation | Yokohama National University(Yokohama Nat. Univ.) |
| 4th Author's Name | Nobuyuki Yoshikawa |
| 4th Author's Affiliation | Yokohama National University(Yokohama Nat. Univ.) |
| Date | 2019-04-19 |
| Paper # | SCE2019-1 |
| Volume (vol) | vol.119 |
| Number (no) | SCE-10 |
| Page | pp.pp.1-6(SCE), |
| #Pages | 6 |
| Date of Issue | 2019-04-12 (SCE) |