| Presentation | 2019-04-18 FPGA prototype of autonomous Time Aware Shaper for low-latency layer 2 switch Kazuto Nishimura, Masaki Hirota, Takafumi Terahara, Hideki Matsui, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In 5th Generation mobile communication, it is considered that Mobile Front Haul (MFH) network is integrated to Layer 2 network because of network efficiency. However, in such a network, MFH traffic may be influenced by other traffic in point of delay. As MFH traffic is delay-sensitive, IEEE802.1-Time Sensitive Networking (TSN) is paid attention because it may achieve low latency communication in packet network. In this paper, we focus on IEEE802.1Qbv (Time Aware Shaper : TAS) which is one of the queueing architecture of TSN. We have proposed the autonomous TAS method called intelligent TAS (iTAS) which could solve the operational problem previously, and have verified the principle of iTAS by using software prototype. In this paper, we implement a part of iTAS function to FPGA and achieve 1000 times more granularityimprovement. This result shows that our method can be applied to actual MFH environment. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low-latency / Layer 2 switch / IEEE802.1 TSN / IEEE802.1Qbv / iTAS / Mobile Front Haul |
| Paper # | CS2019-5 |
| Date of Issue | 2019-04-11 (CS) |
| Conference Information | |
| Committee | CS / CQ |
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| Conference Date | 2019/4/18(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Osaka Univ. Library |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Optical/Wireless Access and Their Integration, QoS and QoE, Assessment / Measurement / Control / Optimization of Communication Quality, Network Services, etc |
| Chair | Hidenori Nakazato(Waseda Univ.) / Takanori Hayashi(Hiroshima Inst. of Tech.) |
| Vice Chair | Jun Terada(NTT) / Hideyuki Shimonishi(NEC) / Jun Okamoto(NTT) |
| Secretary | Jun Terada(NTT) / Hideyuki Shimonishi(Waseda Univ.) / Jun Okamoto(NTT) |
| Assistant | Kazutaka Hara(NTT) / Kentaro Toyoda(Keio Univ.) / Chikara Sasaki(KDDI Research) / Yoshiaki Nishikawa(NEC) / Ryo Yamamoto(UEC) |
| Paper Information | |
| Registration To | Technical Committee on Communication Systems / Technical Committee on Communication Quality |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA prototype of autonomous Time Aware Shaper for low-latency layer 2 switch |
| Sub Title (in English) | |
| Keyword(1) | Low-latency |
| Keyword(2) | Layer 2 switch |
| Keyword(3) | IEEE802.1 TSN |
| Keyword(4) | IEEE802.1Qbv |
| Keyword(5) | iTAS |
| Keyword(6) | Mobile Front Haul |
| 1st Author's Name | Kazuto Nishimura |
| 1st Author's Affiliation | Fujitsu LTD(Fujitsu) |
| 2nd Author's Name | Masaki Hirota |
| 2nd Author's Affiliation | Fujitsu LTD(Fujitsu) |
| 3rd Author's Name | Takafumi Terahara |
| 3rd Author's Affiliation | Fujitsu LTD(Fujitsu) |
| 4th Author's Name | Hideki Matsui |
| 4th Author's Affiliation | Fujitsu LTD(Fujitsu) |
| Date | 2019-04-18 |
| Paper # | CS2019-5 |
| Volume (vol) | vol.119 |
| Number (no) | CS-6 |
| Page | pp.pp.25-30(CS), |
| #Pages | 6 |
| Date of Issue | 2019-04-11 (CS) |