| Presentation | 2019-03-06 Evaluation of an FPGA Implementation of MRCoHOG Feature using High-Level Synthesis Yuya Nagamine, Kazuki Yoshihiro, Hakaru Tamukoh, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, we evaluate a Field Programmable Gate Array (FPGA) implementation of Multiresolution Co-occurrence Histograms of Oriented Gradients (MRCoHOG). MRCoHOG is an image feature that isextracted from multi-resolution images and described by co-occurrence histograms of gradients. We synthesis anMRCoHOG circuit using High-Level Synthesis (HLS) and implement the circuit in an FPGA board. Experimentalresults show that the MRCoHOG circuit performs four times faster operation speed than a software implementation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Feature extraction / Human detection / Image processing / Digital hardware / FPGA / HLS |
| Paper # | SIS2018-37 |
| Date of Issue | 2019-02-27 (SIS) |
| Conference Information | |
| Committee | SIS |
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| Conference Date | 2019/3/6(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tokyo Univ. Science, Katsushika Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Soft Computing, etc. |
| Chair | Takayuki Nakachi(NTT) |
| Vice Chair | Noriaki Suetake(Yamaguchi Univ.) / Tomoaki Kimura(Kanagawa Inst. of Tech.) |
| Secretary | Noriaki Suetake(Kyushu Inst. of Tech.) / Tomoaki Kimura(Tokyo Metropolitan Univ.) |
| Assistant | Takanori Koga(National Inst. of Tech. Tokuyama College) / Hideaki Misawa(National Inst. of Tech., Ube College) |
| Paper Information | |
| Registration To | Technical Committee on Smart Info-Media Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of an FPGA Implementation of MRCoHOG Feature using High-Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | Feature extraction |
| Keyword(2) | Human detection |
| Keyword(3) | Image processing |
| Keyword(4) | Digital hardware |
| Keyword(5) | FPGA |
| Keyword(6) | HLS |
| 1st Author's Name | Yuya Nagamine |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Kazuki Yoshihiro |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Hakaru Tamukoh |
| 3rd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2019-03-06 |
| Paper # | SIS2018-37 |
| Volume (vol) | vol.118 |
| Number (no) | SIS-473 |
| Page | pp.pp.1-4(SIS), |
| #Pages | 4 |
| Date of Issue | 2019-02-27 (SIS) |