| Presentation | 2019-03-18 A Speed-up Method for PLCs(5) Yumeharu Kaji, Yuki Horiguchi, Yukihiro Iguchi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a speed-up method for PLCs (Programmable Logic Controllers) by only modifying programcodes. Ladder diagram (ladder logic) is widely used to PLCs. The idea of the speed-up method is simple: (1) Weconvert ladder diagrams to sequence instructions. (2) Sequence instructions have many logic devices which have valueseither 0 or 1. Assume that a logic device Mi has the value 0 (1), we can reduce some subsequent logical instructionswhich involves Mi. We pregenerate two reduced sequences; one is the codes in which Mi is assigned to 0, the other isthe codes in which Mi is assigned to 1. (3) We connect them using a CJ (conditional jump) operation. Preliminaryexperimental results show that the number of executed instructions is reduced by 3.0～ 4.7 percent. Although thenaive method increases the number of total instructions by 6.3 times. By eliminating duplicate instructions, we preventthe rate of increase by 2.9 times. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PLC(Programmable Logic Controller), / プリコンピューティング |
| Paper # | CPSY2018-121,DC2018-103 |
| Date of Issue | 2019-03-10 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2019/3/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nishinoomote City Hall (Tanega-shima) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2019 |
| Chair | Koji Nakano(Hiroshima Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Yutaka Tamiya(Fujitsu Lab.) / / Masahiro Goshima(NII) |
| Vice Chair | Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Hiroshi Takahashi(Tokyo Inst. of Tech.) / (Nihon Univ.) / (NEC) / (Kochi Univ. of Tech.) |
| Assistant | Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Speed-up Method for PLCs(5) |
| Sub Title (in English) | Reduction of Number Executed Instructions by Precomputing |
| Keyword(1) | PLC(Programmable Logic Controller), |
| Keyword(2) | プリコンピューティング |
| 1st Author's Name | Yumeharu Kaji |
| 1st Author's Affiliation | Meiji University(Meiji Univ.) |
| 2nd Author's Name | Yuki Horiguchi |
| 2nd Author's Affiliation | Meiji University(Meiji Univ.) |
| 3rd Author's Name | Yukihiro Iguchi |
| 3rd Author's Affiliation | Meiji University(Meiji Univ.) |
| Date | 2019-03-18 |
| Paper # | CPSY2018-121,DC2018-103 |
| Volume (vol) | vol.118 |
| Number (no) | CPSY-514,DC-515 |
| Page | pp.pp.341-346(CPSY), pp.341-346(DC), |
| #Pages | 6 |
| Date of Issue | 2019-03-10 (CPSY, DC) |