| Presentation | 2019-03-18 A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semiconductor technologies, it is increasing in defects whose detection is difficult in testing using conventional fault models. One of such defects is modeled by resistive open fault model. Resistive open faults represent degradation in conductivity within circuit's interconnects and result in small delay faults that causing timing failures. The size of an additional delay at a resistive open fault is determined by the effect of the adjacent lines. Therefore, it is important to consider adjacent lines and fault propagation paths in test generation for resistive open faults. In this paper, we propose a test generation method for resistive open faults which considers the number of reversed phase transitions on adjacent lines and the number of sensitized lines for fault propagation using MAX-SAT. Moreover, we evaluate the properties of generated test patterns. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | resistive open faults / MAX-SAT / test generation / adjacent lines |
| Paper # | CPSY2018-117,DC2018-99 |
| Date of Issue | 2019-03-10 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2019/3/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nishinoomote City Hall (Tanega-shima) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2019 |
| Chair | Koji Nakano(Hiroshima Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Yutaka Tamiya(Fujitsu Lab.) / / Masahiro Goshima(NII) |
| Vice Chair | Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Hiroshi Takahashi(Tokyo Inst. of Tech.) / (Nihon Univ.) / (NEC) / (Kochi Univ. of Tech.) |
| Assistant | Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem |
| Sub Title (in English) | |
| Keyword(1) | resistive open faults |
| Keyword(2) | MAX-SAT |
| Keyword(3) | test generation |
| Keyword(4) | adjacent lines |
| 1st Author's Name | Hiroshi Yamazaki |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| 4th Author's Name | Masayuki Arai |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| 5th Author's Name | Hiroyuki Yotsuyanagi |
| 5th Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 6th Author's Name | Masaki Hashizume |
| 6th Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2019-03-18 |
| Paper # | CPSY2018-117,DC2018-99 |
| Volume (vol) | vol.118 |
| Number (no) | CPSY-514,DC-515 |
| Page | pp.pp.315-320(CPSY), pp.315-320(DC), |
| #Pages | 6 |
| Date of Issue | 2019-03-10 (CPSY, DC) |