| Presentation | 2019-03-17 Design of Vector Unit for AI Acceleration in Embedded Processor Yosuke Ide, Hiromi Suzuki, Yuki Mori, Nobuyuki Yamasaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, AI is applied in wide range of fields. Its learning and recognition are based on Neural Network (NN), which are actively studied. Although for High-Performance Computing (HPC), GPU, FPGA or ASIC specialized to certain NN is proposed, it is not easy to apply them to embedded applications because of power consumption and area constraints. On the other hand, some embedded processors adopt vector units for multimedia application. In this study, extended vector load function and lower precision SIMD operation are added to vector units to accelerate convolution, which is executed in Convolutional Neural Network. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded Processor / Vector Unit / Convolutionanl Neural Network / AI |
| Paper # | CPSY2018-107,DC2018-89 |
| Date of Issue | 2019-03-10 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2019/3/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nishinoomote City Hall (Tanega-shima) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2019 |
| Chair | Koji Nakano(Hiroshima Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Yutaka Tamiya(Fujitsu Lab.) / / Masahiro Goshima(NII) |
| Vice Chair | Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Hiroshi Takahashi(Ehime Univ.) |
| Secretary | Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Hiroshi Takahashi(Tokyo Inst. of Tech.) / (Nihon Univ.) / (NEC) / (Kochi Univ. of Tech.) |
| Assistant | Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Vector Unit for AI Acceleration in Embedded Processor |
| Sub Title (in English) | |
| Keyword(1) | Embedded Processor |
| Keyword(2) | Vector Unit |
| Keyword(3) | Convolutionanl Neural Network |
| Keyword(4) | AI |
| 1st Author's Name | Yosuke Ide |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Hiromi Suzuki |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| 3rd Author's Name | Yuki Mori |
| 3rd Author's Affiliation | Keio University(Keio Univ.) |
| 4th Author's Name | Nobuyuki Yamasaki |
| 4th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2019-03-17 |
| Paper # | CPSY2018-107,DC2018-89 |
| Volume (vol) | vol.118 |
| Number (no) | CPSY-514,DC-515 |
| Page | pp.pp.167-172(CPSY), pp.167-172(DC), |
| #Pages | 6 |
| Date of Issue | 2019-03-10 (CPSY, DC) |