| Presentation | 2019-02-27 Set-Pair Routing Algorithm with Selective Pin-Pair Connections Kano Akagi, Shimpei Sato, Atsushi Takahashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a set-pair routing algorithm which efficiently generates a length matched routing pattern. In our algorithm, first, a target pin-pairs set which is a set of pin-pairs expected to generate a length matched routing pattern is selected. Then, a routing pattern is generated so as to connect the target pin-pairs as much as possible. As the target pin-pairs set, a set of pin-pairs whose maximum distance is minimum and the minimum distance is maximum is selected. Pin-pairs to be connected may be different from the target pin-pairs. However, every wire is generated so as not to interfere with other connections in order to realize the target pin-pair connections as much as possible. In experiments, it is confirmed that routing patterns which are comparable to routing patterns obtained by existing method are generated in short computation time by our algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Set-Pair Routing / Target Pin-Pair / Routing Algorithm |
| Paper # | VLD2018-99,HWS2018-62 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2019/2/27(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Tsutomu Matsumoto(Yokohama National Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Vice Chair | Shinichi Kawamura(Toshiba) / Makoto Ikeda(Univ. of Tokyo) / Nozomu Togawa(Waseda Univ.) |
| Secretary | Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM) / Nozomu Togawa(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Set-Pair Routing Algorithm with Selective Pin-Pair Connections |
| Sub Title (in English) | |
| Keyword(1) | Set-Pair Routing |
| Keyword(2) | Target Pin-Pair |
| Keyword(3) | Routing Algorithm |
| 1st Author's Name | Kano Akagi |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Shimpei Sato |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Atsushi Takahashi |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2019-02-27 |
| Paper # | VLD2018-99,HWS2018-62 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-457,HWS-458 |
| Page | pp.pp.37-42(VLD), pp.37-42(HWS), |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |