| Presentation | 2019-03-01 Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs Sayuri Ota, Nagisa Ishiura, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This article presents a method for synthesizing circuits with distributed control from CDFGs (control data flow graphs). The distributed control attempts to harness a datapath with multiple FSMs (finite state machines) to adjust execution timing of operations dynamically, by which wasteful waits caused by variable latency units are reduced. Although Shimizu and Nakano proposed a distributed control scheme which allowed dynamic scheduling across multiple DFGs, they just presented example controllers which were manually designed. This article shows a formulation to make the multiple FSMs work in ensemble based on Nakano’s scheme, along with some restrictions on CDFGs to allow automatic synthesis. Experimental results shows that the synthesized circuits are on average about 13% larger than those based on conventional centralized controllers, but the critical path delay stays the same. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis / variable latency units / control synthesis / distributed controller |
| Paper # | VLD2018-125,HWS2018-88 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
|---|---|
| Conference Date | 2019/2/27(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Tsutomu Matsumoto(Yokohama National Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Vice Chair | Shinichi Kawamura(Toshiba) / Makoto Ikeda(Univ. of Tokyo) / Nozomu Togawa(Waseda Univ.) |
| Secretary | Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM) / Nozomu Togawa(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | variable latency units |
| Keyword(3) | control synthesis |
| Keyword(4) | distributed controller |
| 1st Author's Name | Sayuri Ota |
| 1st Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| Date | 2019-03-01 |
| Paper # | VLD2018-125,HWS2018-88 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-457,HWS-458 |
| Page | pp.pp.193-198(VLD), pp.193-198(HWS), |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |