| Presentation | 2019-03-02 ASIC Chip Implementation and Evaluation of Elliptic Curve Digital Signature Algorithm Sosuke Sato, Hiroki Yoshida, Kazuki Monta, Takaaki Okidono, Takuji Miki, Noriyuki Miura, Makoto Nagata, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have designed and fabricated application specific semiconductor integrated circuit (ASIC) chips that embody the generation and verification functions based on elliptic curve digital signature algorithm. A 0.13 nm CMOS technology was used. An evaluation system for ECDSA chip has been constructed. This paper reports overviews of the designed ASIC chips and initial results of evaluation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Semiconductor integrated circuits / Cryptographic integrated circuits / Digital signature / Semiconductor IC chip |
| Paper # | VLD2018-138,HWS2018-101 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2019/2/27(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Tsutomu Matsumoto(Yokohama National Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Vice Chair | Shinichi Kawamura(Toshiba) / Makoto Ikeda(Univ. of Tokyo) / Nozomu Togawa(Waseda Univ.) |
| Secretary | Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM) / Nozomu Togawa(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ASIC Chip Implementation and Evaluation of Elliptic Curve Digital Signature Algorithm |
| Sub Title (in English) | |
| Keyword(1) | Semiconductor integrated circuits |
| Keyword(2) | Cryptographic integrated circuits |
| Keyword(3) | Digital signature |
| Keyword(4) | Semiconductor IC chip |
| 1st Author's Name | Sosuke Sato |
| 1st Author's Affiliation | Kobe University(Kobe Univ.) |
| 2nd Author's Name | Hiroki Yoshida |
| 2nd Author's Affiliation | Kobe University(Kobe Univ.) |
| 3rd Author's Name | Kazuki Monta |
| 3rd Author's Affiliation | Kobe University(Kobe Univ.) |
| 4th Author's Name | Takaaki Okidono |
| 4th Author's Affiliation | ECSEC(ECSEC) |
| 5th Author's Name | Takuji Miki |
| 5th Author's Affiliation | Kobe University(Kobe Univ.) |
| 6th Author's Name | Noriyuki Miura |
| 6th Author's Affiliation | Kobe University(Kobe Univ.) |
| 7th Author's Name | Makoto Nagata |
| 7th Author's Affiliation | Kobe University(Kobe Univ.) |
| Date | 2019-03-02 |
| Paper # | VLD2018-138,HWS2018-101 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-457,HWS-458 |
| Page | pp.pp.267-269(VLD), pp.267-269(HWS), |
| #Pages | 3 |
| Date of Issue | 2019-02-20 (VLD, HWS) |