| Presentation | 2019-03-01 A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs Tatsuki Otake, Hiroshi Saito, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this work, we study placement constraints for asynchronous circuits with bundled-data implemen-tation aimed for Field Programmable Gate Arrays (FPGAs) to reduce the number of delay adjustments and to improve circuit performance. Placement constraints studied in this work are the placement constraints which can be used in a design tool supported by an FPGA vendor. In the experiment, we applied the placement constraints to two circuits and evaluated the number of delay adjustments, circuit performance, area, power consumption, and energy consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous circuits / FPGA / Placement constraints |
| Paper # | VLD2018-123,HWS2018-86 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2019/2/27(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Tsutomu Matsumoto(Yokohama National Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Vice Chair | Shinichi Kawamura(Toshiba) / Makoto Ikeda(Univ. of Tokyo) / Nozomu Togawa(Waseda Univ.) |
| Secretary | Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM) / Nozomu Togawa(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuits |
| Keyword(2) | FPGA |
| Keyword(3) | Placement constraints |
| 1st Author's Name | Tatsuki Otake |
| 1st Author's Affiliation | University of Aizu(UoA) |
| 2nd Author's Name | Hiroshi Saito |
| 2nd Author's Affiliation | University of Aizu(UoA) |
| Date | 2019-03-01 |
| Paper # | VLD2018-123,HWS2018-86 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-457,HWS-458 |
| Page | pp.pp.181-186(VLD), pp.181-186(HWS), |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |