| Presentation | 2019-03-01 Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a method of automatically synthesizing a hardwaredesign from a set of source codes for a real-time system utilizing anRTOS. It generates a full hardware implementation where all thetasks and handlers in the system as well as all the necessary servicesprovided by the RTOS kernel are implemented as hardware. Every taskand handler is synthesized into an independent hardware module so thatit may run in parallel with the other tasks/handlers as soon as it isready. This leads to task switching with extremely low overhead andreduced computation time both by parallel and hardware execution. Moreover, this eliminates the necessity of the task queue management;task scheduling is realized by a relatively simple manager hardwarewhich instructs each task/handler to run or stall based on the valuesof its status variables. Since most of the API calls fromtasks/handlers are reduced to reads/writes of these status variables, they can be expanded inline into the tasks/handlers' source codeswhich are compiled into hardware designs by a high-level synthesizer. We have implemented a prototype synthesis system which assume the useof the TOPPERS/ASP3 real-time kernel. A hardware implementationsynthesized from a sample1.c code, bundled in the TOPPERS/ASP3release, took 23 cycles for waking up a waiting task and only 1 cyclefor activating an interrupt handler. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Real-Time Systems / RTOS / System Synthesis / Hardware Accelerator / TOPPERS/ASP3 / High-Level Synthesis |
| Paper # | VLD2018-122,HWS2018-85 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2019/2/27(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Tsutomu Matsumoto(Yokohama National Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Vice Chair | Shinichi Kawamura(Toshiba) / Makoto Ikeda(Univ. of Tokyo) / Nozomu Togawa(Waseda Univ.) |
| Secretary | Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM) / Nozomu Togawa(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Synthesis of Full Hardware Implementation of RTOS-Based Systems |
| Sub Title (in English) | |
| Keyword(1) | Real-Time Systems |
| Keyword(2) | RTOS |
| Keyword(3) | System Synthesis |
| Keyword(4) | Hardware Accelerator |
| Keyword(5) | TOPPERS/ASP3 |
| Keyword(6) | High-Level Synthesis |
| 1st Author's Name | Yuuki Oosako |
| 1st Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 3rd Author's Name | Hiroyuki Tomiyama |
| 3rd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 4th Author's Name | Hiroyuki Kanbara |
| 4th Author's Affiliation | ASTEM RI(ASTEM) |
| Date | 2019-03-01 |
| Paper # | VLD2018-122,HWS2018-85 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-457,HWS-458 |
| Page | pp.pp.175-180(VLD), pp.175-180(HWS), |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |