| Presentation | 2019-02-28 High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology Kazuki Niino, Takashi Imagawa, Hiroyuki Ochi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Domino logic was introduced at the forefront of the LSI market in the 2000s for high-speed circuits. In recent years, however, domino logic has been rarely introduced due to the unreliability factors such as large dynamic power and exponential increase of leakage current induced by the progress of fabrication technology. On the other hand, siliconon thin buried oxide (SOTB) has attracted attention as a new CMOS process technology. SOTB is a type of fully depleted silicon-on-insulator (FD-SOI), and its parasitic capacitance and leakage current are small due to its structure. In this report, we propose a high-radix tree adder that exploits these features of SOTB. To improve the performance of the proposed adder, we explore an appropriate transistor sizing based on the analysis of unreliability factors. The evaluation result shows that the delay of the proposed 23-bit, 64-bit high-radix tree adders are 3.2% and 1.8% smaller than that of the radix-2 tree adder, respectively. Moreover, by comparison with bulk CMOS, it showed high affinity of SOTB and domino logic. The 16-bit multiplier with the proposed adders shows 27.4% to 34.3% smaller delay than that of the standard-cell-based static CMOS designed by Synopsys Design Compiler. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | domino logic / SOTB / leakage current / keeper / multiplier |
| Paper # | VLD2018-112,HWS2018-75 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
| Conference Information | |
| Committee | HWS / VLD |
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| Conference Date | 2019/2/27(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Chair | Tsutomu Matsumoto(Yokohama National Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Vice Chair | Shinichi Kawamura(Toshiba) / Makoto Ikeda(Univ. of Tokyo) / Nozomu Togawa(Waseda Univ.) |
| Secretary | Shinichi Kawamura(Kobe Univ.) / Makoto Ikeda(SECOM) / Nozomu Togawa(NTT) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Hardware Security / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology |
| Sub Title (in English) | |
| Keyword(1) | domino logic |
| Keyword(2) | SOTB |
| Keyword(3) | leakage current |
| Keyword(4) | keeper |
| Keyword(5) | multiplier |
| 1st Author's Name | Kazuki Niino |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 2nd Author's Name | Takashi Imagawa |
| 2nd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 3rd Author's Name | Hiroyuki Ochi |
| 3rd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| Date | 2019-02-28 |
| Paper # | VLD2018-112,HWS2018-75 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-457,HWS-458 |
| Page | pp.pp.115-120(VLD), pp.115-120(HWS), |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |