| Presentation | 2019-01-23 Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka, Yuki Hatanaka, Yuichi Matsui, Koki Ishida, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Takatsugu Ono, Koji Inoue, Akira Fujimaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughput performance beyond CMOS microprocessors. All of the demonstrated microprocessors based on SFQ logic employed bit-serial processing. The bit-serial processing leads to reduction of complexity and ease of design, but it limits throughput. It is necessary to introduce bit-parallel processing for obtaining higher throughput beyond CMOS microprocessors. We can expect significant improvement in the throughput performance by introducing bit-parallel processing and a gate-level pipelined structure, in which pipeline processing is performed logic gate by logic gate. In this study, to realize bit-parallel SFQ microprocessors, we designed and evaluated a datapath that was the most complex circuit in a microprocessor. We integrated an arithmetic logic unit (ALU) and a register file to increase the operation frequency. We confirmed correct operation of addition and subtraction instructions and part of write-back operation of the register file up to approximately 30GHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ circuit / Micorprocessor / Gate-level-pipeline / Bit-parallel processing |
| Paper # | SCE2018-30 |
| Date of Issue | 2019-01-16 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2019/1/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Hiroaki Myoren(Saitama Univ.) |
| Vice Chair | |
| Secretary | (Nagoya Univ.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors |
| Sub Title (in English) | |
| Keyword(1) | SFQ circuit |
| Keyword(2) | Micorprocessor |
| Keyword(3) | Gate-level-pipeline |
| Keyword(4) | Bit-parallel processing |
| 1st Author's Name | Ikki Nagaoka |
| 1st Author's Affiliation | Nagoya University(Nagoya Univ) |
| 2nd Author's Name | Yuki Hatanaka |
| 2nd Author's Affiliation | Mitsubishi Electric(Mitsubishi Elec) |
| 3rd Author's Name | Yuichi Matsui |
| 3rd Author's Affiliation | Nagoya University(Nagoya Univ) |
| 4th Author's Name | Koki Ishida |
| 4th Author's Affiliation | Kyushu University(Kyushu Univ) |
| 5th Author's Name | Masamitsu Tanaka |
| 5th Author's Affiliation | Nagoya University(Nagoya Univ) |
| 6th Author's Name | Kyosuke Sano |
| 6th Author's Affiliation | Nagoya University(Nagoya Univ) |
| 7th Author's Name | Taro Yamashita |
| 7th Author's Affiliation | Nagoya University(Nagoya Univ) |
| 8th Author's Name | Takatsugu Ono |
| 8th Author's Affiliation | Kyushu University(Kyushu Univ) |
| 9th Author's Name | Koji Inoue |
| 9th Author's Affiliation | Kyushu University(Kyushu Univ) |
| 10th Author's Name | Akira Fujimaki |
| 10th Author's Affiliation | Nagoya University(Nagoya Univ) |
| Date | 2019-01-23 |
| Paper # | SCE2018-30 |
| Volume (vol) | vol.118 |
| Number (no) | SCE-415 |
| Page | pp.pp.29-34(SCE), |
| #Pages | 6 |
| Date of Issue | 2019-01-16 (SCE) |