Information and Systems-Speech(Date:2001/10/19)

Presentation
表紙

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[Date]2001/10/19
[Paper #]
目次

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[Date]2001/10/19
[Paper #]
Performance Evaluation of Wave-Pipelines and Conventional Pipelines

Masa-aki Fukase,  Ryusuke Egawa,  Tomoaki Sato,  Syunsuke Itoh,  Tadao Nakamura,  

[Date]2001/10/19
[Paper #]DSP2001-110,ICD2001-115,IE2001-94
Desgin of a VLSI Image Processor Based on a Periodical Memory Allocation

Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2001/10/19
[Paper #]DSP2001-111,ICD2001-116,IE2001-95
Improvement of the AES cryptography circuit using FPGA

Hidenori SEIKE,  Takakazu KUROKAWA,  

[Date]2001/10/19
[Paper #]DSP2001-112,ICD2001-117,IE2001-96
An implementation of the dynamically reconfigurable CPU corresponding to application programs

Hiroyuki Noge,  Takakazu Kurokawa,  

[Date]2001/10/19
[Paper #]DSP2001-113,ICD2001-118,IE2001-97
Parallel Processing of One-sided Radon Transform for the Detection of the Position and the Orientation of Planar Motion Objects

Shinichi HIRAI,  Tatsuhiko TSUBOI,  Akihiko MASUBUCHI,  Masakazu ZAKOUJI,  

[Date]2001/10/19
[Paper #]DSP2001-114,ICD2001-119,IE2001-98
QVGA/CIF Resolution MPEG-4 Video Codec Based on A Low Power DSP

Atsushi HATABU,  Takashi MIYAZAKI,  Ichiro KURODA,  

[Date]2001/10/19
[Paper #]DSP2001-115,ICD2001-120,IE2001-99
Still Image Processing Having Very High Compression Ratio and Quality Using Adaptive Resolution Vector Quantization Technology

T. Nakayama,  T. Nozawa,  M. Fujibayashi,  K. Mochizuki,  M. Konda,  K. Kotani,  S. Sugawa,  T. Ohmi,  

[Date]2001/10/19
[Paper #]DSP2001-116,ICD2001-121,IE2001-100
Development of Image Processing LSI based on Phase Only Correlation

Makoto MORIKAWA,  Atsushi KATSUMATA,  Koji KOBAYASHI,  

[Date]2001/10/19
[Paper #]DSP2001-117,ICD2001-122,IE2001-101
Design of a Multiple-Valued Domino Integrated Circuit Based on Source-Coupled Logic

Takayoshi MOCHIZUKI,  Takahiro HANYU,  Michitaka KAMEYAMA,  

[Date]2001/10/19
[Paper #]DSP2001-118,ICD2001-123,IE2001-102
A Low-Power, High-Speed, Small, 0.13-μm CMOS Square Root Circuit

Chihiro Oda,  Hiroaki Shikano,  Tomochika Harada,  Tadayoshi Enomoto,  

[Date]2001/10/19
[Paper #]DSP2001-119,ICD2001-124,IE2001-103
A Technique to Suppress Performance Degradation on VT-CMOS Data Cache using Address Prediction

Ryo FUJIOKA,  Kiyokazu KATAYAMA,  Ryotaro KOBAYASHI,  Hideki ANDO,  Toshio SHIMADA,  

[Date]2001/10/19
[Paper #]DSP2001-120,ICD2001-125,IE2001-104
An Area-Effective Superscalar Datapath Architecture Suitable for Embedded Multimedia Processors

Toshiaki INOUE,  Takashi MANABE,  Sunao TORII,  Satoshi MATSUSHITA,  Masato EDAHIRO,  Naoki NISHI,  Masakazu YAMASHINA,  

[Date]2001/10/19
[Paper #]DSP2001-1121,ICD2001-126,IE2001-105
Improvement on SIMD Macroblock Processor in MPEG-2 Video Encoder LSI

Koyo NITTA,  Yasuhiko SATOH,  Takeshi YOSHITOME,  Toshio KONDO,  

[Date]2001/10/19
[Paper #]DSP2001-122,ICD2001-127,IE2001-106
The Haar-Wavelet Transform Chip Performs Picture Analysis on a Partial Selection Target

Mutsuki NIKI,  Masatoshi SEKINE,  Hikaru ITOH,  Toshiaki KOBA,  

[Date]2001/10/19
[Paper #]DSP2001-123,ICD2001-128,IE2001-107
High Performance DSP Architecture with Quadruple MACs

Daiji ISHII,  Masao IKEKAWA,  Ichiro KURODA,  

[Date]2001/10/19
[Paper #]DSP2001-124,ICD2001-129,IE2001-108
[OTHERS]

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[Date]2001/10/19
[Paper #]