IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2023/01/23)

Presentation

Yuho Taira(Okisho HS), Yasunori Osana(UR),

[Date]2023-01-23
[Paper #]VLD2022-61,RECONF2022-84

Evaluation of reduced routing resources for HPC-Oriented CGRAs

Carlos Cortes(RIKEN Center for Computational Science (R-CCS)), Boma Adhi(RIKEN Center for Computational Science (R-CCS)), Tomohiro Ueno(RIKEN Center for Computational Science (R-CCS)), Yiyu Tan(Dept of Systems Innovation Engineering Iwate Univ.), Takuya Kojima(Information Science and Technology The Univ. of Tokyo), Artur Podobas(KTH Royal Inst. of Technology), Kentaro Sato(RIKEN Center for Computational Science (R-CCS)),

[Date]2023-01-23
[Paper #]VLD2022-59,RECONF2022-82

Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder

Junpei Sanuki(HCU), Ibuki Watanabe(HCU), Atsushi Kubota(HCU), Tetsuo Hironaka(HCU),

[Date]2023-01-23
[Paper #]VLD2022-58,RECONF2022-81

A study on optimisation of Back Projection Processing of CT Images using FPGA

Jumpei Mano(Meiji Univ), Takaaki Miyajima(Meiji Univ), Peng Chen(AIST), Mohamed Wahib(RIKEN), Kentaro Sano(RIKEN),

[Date]2023-01-23
[Paper #]VLD2022-63,RECONF2022-86

Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool

Hiroaki Suzuki(Keio Univ), Wataru Takahashi(NEC), Kazutoshi Wakabayashi(Tokyo Univ), Hideharu Amano(Keio Univ),

[Date]2023-01-23
[Paper #]VLD2022-56,RECONF2022-79

FPGA搭載ミニ四駆の試作

Tomonori Izumi(Ritsumeikan Univ.),

[Date]2023-01-23
[Paper #]VLD2022-64,RECONF2022-87

Interface development for Python use of FPGA cluster ESSPER

Taiki Watanabe(TUT), Kentaro Sano(R-CCS), Yukinori Sato(TUT),

[Date]2023-01-23
[Paper #]VLD2022-62,RECONF2022-85

Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA)

Kazuki Yaguchi(TUAT), Eriko Maeda(TUAT), Daichi Teruya(TUAT), Yasunori Osana(Univ. of the Ryukyus), Takefumi Miyoshi(WasaLabo), Hironori Nakajo(TUAT),

[Date]2023-01-23
[Paper #]VLD2022-57,RECONF2022-80

[Invited Talk] Can we say "No FPGA, No Smart City"?

Hiroaki Nishi(Keio Univ.),

[Date]2023-01-23
[Paper #]VLD2022-60,RECONF2022-83

Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM

Motoki Kamibayashi(Kyoto Inst. of Tech.), Kazutoshi Kobayashi(Kyoto Inst. of Tech.), Masanori Hashimoto(Kyoto Univ.),

[Date]2023-01-24
[Paper #]VLD2022-65,RECONF2022-88

Kyokkoへの仮想チャネル機能の実装

Akinobu Tomori(Univ. Ryukyu), Yasunori Osana(Univ. Ryukyus),

[Date]2023-01-24
[Paper #]VLD2022-69,RECONF2022-92

Leveraging dynamic parameter for solution search acceleration in bio-inspired hardware SAT solver

Anh Hoang Ngoc Nguyen(Fujitsu ltd.),

[Date]2023-01-24
[Paper #]VLD2022-71,RECONF2022-94

An Implementation of Generic IP-cores for Linux by Using VIRTIO Interface

Kota Asanuma(TUAT/e-trees), Takefumi Miyoshi(e-trees),

[Date]2023-01-24
[Paper #]VLD2022-70,RECONF2022-93

Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree

Takahiro Tanigawa(Kwansei Gakuin Univ.), Mugi Noda(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.),

[Date]2023-01-24
[Paper #]VLD2022-68,RECONF2022-91

Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips

Chiharu Shiro(Ritsumeiakn Univ.), Hiroki Nishikawa(Osaka Univ.), Xiangbo Kong(Ritsumeiakn Univ.), Hiroyuki Tomiyama(Ritsumeiakn Univ.), Shigeru Yamashita(Ritsumeiakn Univ.),

[Date]2023-01-24
[Paper #]VLD2022-67,RECONF2022-90

Study on Wireless Transmission Data Reduction Method and Its Implementation in Emotion Recognition System Using Electroencephalogram

Yuuki Harada(Osaka Univ.), Daisuke Kanemoto(Osaka Univ.), Tetsuya Hirose(Osaka Univ.),

[Date]2023-01-24
[Paper #]VLD2022-66,RECONF2022-89

Implementing a quantum computer simulator Qulacs on FPGAs

Hideharu Amano(Keio Univ.), Wei Kaijie(Keio Univ.), Takefumi Miyoshi(Wasalab.), Yoshiki Yamaguchi(U.niv. of Tsukuba), Ryohei Niwase(U.niv. of Tsukuba),

[Date]2023-01-24
[Paper #]VLD2022-72,RECONF2022-95