Information and Systems-Reconfigurable Systems(Date:2021/01/25)

Presentation
Implementation of Quantized Deep Neural Network on FPGA

Pan Hongyi(AIST/The Univ. of Tokyo),  Ben Ahmed Akram(AIST),  Ikegami Tsutomu(AIST),  Tominaga Kazuki(The Univ. of Tokyo),  Kudoh Tomohiro(AIST/The Univ. of Tokyo),  

[Date]2021-01-25
[Paper #]VLD2020-50,CPSY2020-33,RECONF2020-69
シストリックリングアレイ(IMAX2)を用いた高効率誤差逆伝播の実装

Hidenari Inamasu(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2021-01-25
[Paper #]VLD2020-45,CPSY2020-28,RECONF2020-64
IMAX2: GTHの8レーン化を契機とするIMAXの倍速化

Yasuhiko Nakashima(NAIST),  

[Date]2021-01-25
[Paper #]VLD2020-44,CPSY2020-27,RECONF2020-63
[Invited Talk] System Architecture and Interconnect Development for the Supercomputer "K" and "Fugaku"

Yuichiro Ajima(Fujitsu),  

[Date]2021-01-25
[Paper #]VLD2020-43,CPSY2020-26,RECONF2020-62
Evaluations of FPGA-based Neural Networks using of ODE

Hirohisa Watanabe(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2021-01-25
[Paper #]VLD2020-47,CPSY2020-30,RECONF2020-66
Residual signed-digit number - residual binary number conversion algorithm

Yuki Saba(Gunma Univ.),  Yuuki Tanaka(Gunma Univ.),  Shugang Wei(Gunma Univ.),  

[Date]2021-01-25
[Paper #]VLD2020-51,CPSY2020-34,RECONF2020-70
High speed architectures of decimal counters

Shuhei Yanagawa(Gunma Univ.),  Yuuki Tanaka(Gunma Univ.),  Shugang Wei(Gunma Univ.),  

[Date]2021-01-25
[Paper #]VLD2020-54,CPSY2020-37,RECONF2020-73
ESSPER：高性能計算のためのスケーラブルかつ柔軟なFPGAクラスタシステムの開発

Kentaro Sano(RIKEN),  Tomohiro Ueno(RIKEN),  Takaaki Miyajima(RIKEN),  Jens Huthmann(RIKEN),  Atsushi Koshiba(RIKEN),  

[Date]2021-01-25
[Paper #]VLD2020-40,CPSY2020-23,RECONF2020-59
Comparison of ICA Algorithms in the Compressed Sensing EEG Measurement Framework Using OD-ICA

Wataru Okumura(Osaka Univ),  Daisuke Kanemoto(Osaka Univ),  Osamu Maida(Osaka Univ),  Tetsuya Hirose(Osaka Univ),  

[Date]2021-01-25
[Paper #]VLD2020-52,CPSY2020-35,RECONF2020-71
キャビネット内通信を考慮した低直径・配置最適な相互結合網の検討

Ryuta Kawano(JAIST),  Hiroki Matsutani(Keio Univ.),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2021-01-25
[Paper #]VLD2020-39,CPSY2020-22,RECONF2020-58
Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method

Hiroki Tada(JAIST),  Tomohiro Ueno(R-CCS),  Atsushi Koshiba(R-CCS),  Kentaro Sano(R-CCS),  Ryuta Kawano(JAIST),  Yasushi Inoguchi(JAIST),  

[Date]2021-01-25
[Paper #]VLD2020-41,CPSY2020-24,RECONF2020-60
A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA

Koki Sayama(Tokyo Tech),  Akira Jinguji(Tokyo Tech),  Naoto Soga(Tokyo Tech),  Hiroki Nakahara(Tokyo Tech),  

[Date]2021-01-25
[Paper #]VLD2020-49,CPSY2020-32,RECONF2020-68
Low Power EEG Measurement Using Compressed Sensing Consideration of the Sampling Interval

Yuki Okabe(Osaka Univ.),  Daisuke Kanemoto(Osaka Univ.),  Tomoya Mochizuki(Yamanashi Univ.),  Osamu Maida(Osaka Univ.),  Tetsuya Hirose(Osaka Univ.),  

[Date]2021-01-25
[Paper #]VLD2020-53,CPSY2020-36,RECONF2020-72
Efficient Attention Mechanism by Softmax Function with Trained Coefficient

Kaito Hirota(UT),  O'uchi Shinichi(AIST),  Fujita Masahiro(UT),  

[Date]2021-01-25
[Paper #]VLD2020-48,CPSY2020-31,RECONF2020-67
An implementation and evaluation of Fast Fourier Transform on FPGA for High-performance Computing

Takaaki Miyajima(RIKEN),  Tomohiro Ueno(RIKEN),  Kentaro Sano(RIKEN),  

[Date]2021-01-25
[Paper #]VLD2020-42,CPSY2020-25,RECONF2020-61
Throughput improvement of Responsive Link with High Speed Transceiver in FPGA

Masahiko Takahashi(Keio Univ.),  Yamasaki Nobuyuki(Keio Univ.),  

[Date]2021-01-25
[Paper #]VLD2020-46,CPSY2020-29,RECONF2020-65
Network Intrusion Detection System based on Hybrid FPGA/GPU Pattern Matching

Shunta Kikuchi(AIST/The Univ. of Tokyo),  Tsutomu Ikegami(AIST),  Akram ben Ahmed(AIST),  Tomohiro Kudoh(The Univ. of Tokyo/AIST),  Ryohei Kobayashi(Univ. of Tsukuba),  Norihisa Fujita(Univ. of Tsukuba),  Taisuke Boku(Univ. of Tsukuba),  

[Date]2021-01-26
[Paper #]VLD2020-59,CPSY2020-42,RECONF2020-78
Acceleration of Database Query Processing Using FPGA

Hirohiko Ozaku(UEC),  Masato Yoshimi(TIS),  Celimuge Wu(UEC),  Tsutomu Yoshinaga(UEC),  

[Date]2021-01-26
[Paper #]VLD2020-55,CPSY2020-38,RECONF2020-74
FPGA Accelerator Design for Real-Time Object Detection

Koichiro Ban(Toshiba),  Masanori Furuta(Toshiba),  Daisuke Kobayashi(Toshiba),  

[Date]2021-01-26
[Paper #]VLD2020-56,CPSY2020-39,RECONF2020-75
FPGA Implementation of Semantic Segmentation on LWIR Images for Autonomous Robot

Yuichiro Niwa(ATLA),  Taiki Fujii(eSOL),  

[Date]2021-01-26
[Paper #]VLD2020-57,CPSY2020-40,RECONF2020-76
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