Information and Systems-Reconfigurable Systems(Date:2018/01/18)

Presentation
All Binarized Conventional Neural Network and its Implementation on an FPGA

Masayuki Shimoda(titech),  Shimpei Sato(titech),  Hiroki Nakahara(titech),  

[Date]2018-01-18
[Paper #]VLD2017-63,CPSY2017-107,RECONF2017-51
密結合FPGAクラスタのための直接網の設計と評価

Daichi Tanaka(Tohoku Univ),  Antoniette Mondigo(Tohoku Univ),  Kentaro Sano(Tohoku Univ),  Satoru Yamamoto(Tohoku Univ),  

[Date]2018-01-18
[Paper #]VLD2017-74,CPSY2017-118,RECONF2017-62
ロボット制御アルゴリズムのFPGAによる専用ハードウェア実装と評価

Shin Abiko(Tohoku Univ.),  Kohei Nagasu(Tohoku Univ.),  Kentaro Sano(Tohoku Univ.),  

[Date]2018-01-18
[Paper #]VLD2017-72,CPSY2017-116,RECONF2017-60
Distributed Memory Architecture for High-Level Synthesis from Erlang

Kagumi Azuma(Kwansei Gakuin Univ.),  Shoki Hamana(Kwansei Gakuin Univ.),  Hidekazu Wakabayashi(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  Nobuaki Yoshida(ASTEM),  Hiroyuki Kanbara(ASTEM),  

[Date]2018-01-18
[Paper #]VLD2017-75,CPSY2017-119,RECONF2017-63
クラウド環境下での仮想ディスクワークロードの取得手法

Kazutaka Ogihara(Fujitsu Lab.),  

[Date]2018-01-18
[Paper #]VLD2017-65,CPSY2017-109,RECONF2017-53
Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs

Kaori Tajima(Fukuoka Univ.),  Masahiro Inoue(Fukuoka Univ.),  Hiroyuki Baba(Fukuoka Univ.),  Tongxin Yang(Fukuoka Univ.),  Tomoaki Ukezono(Fukuoka Univ.),  Toshinori Sato(Fukuoka Univ.),  

[Date]2018-01-18
[Paper #]VLD2017-68,CPSY2017-112,RECONF2017-56
Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set

Kouhei Yamazaki(Gunma Univ.),  Yuuki Tanaka(Gunma Univ.),  Shugang Wei(Gunma Univ.),  

[Date]2018-01-18
[Paper #]VLD2017-69,CPSY2017-113,RECONF2017-57
マルチFPGAボードによるRecurrent Neural Networkの高速化

Yugo Yamauchi(Keio Univ.),  Kazusa Musha(Keio Univ.),  Kudoh Tomohiro(Univ. of Tokyo),  Hideharu Amano(Keio Univ.),  

[Date]2018-01-18
[Paper #]VLD2017-62,CPSY2017-106,RECONF2017-50
Integrated Machine Code Monitor on FPGA

Hiroaki Kaneko(TokyoDenki Univ.),  Akinori Kanasugi(TokyoDenki Univ.),  

[Date]2018-01-18
[Paper #]VLD2017-73,CPSY2017-117,RECONF2017-61
時分割多重実行型シストリックリングの実装と評価

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[Date]2018-01-18
[Paper #]VLD2017-67,CPSY2017-111,RECONF2017-55
An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL

Takumu Uyama(Titech),  Tomoya Fujii(Titech),  Haruyoshi Yonekawa(Titech),  Shimpei Sato(Titech),  Hiroki Nakahara(Titech),  

[Date]2018-01-18
[Paper #]VLD2017-64,CPSY2017-108,RECONF2017-52
3次元DRAM-プロセッサ積層の温度と性能

Naoya Niwa(Keio Univ.),  Tomohiro Totoki(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2018-01-18
[Paper #]VLD2017-66,CPSY2017-110,RECONF2017-54
Examination of the Normally-off using the stack circuit

Kenji Sakamura(OPUGS),  Kazutami Arimoto(OPU),  Isao Kayano(OPU),  Tomoyuki Yokogawa(OPU),  

[Date]2018-01-18
[Paper #]VLD2017-70,CPSY2017-114,RECONF2017-58
[Fellow Memorial Lecture] A Study on Interconnection Networks and Their Computing Systems

Tsutomu Yoshinaga(UEC),  

[Date]2018-01-18
[Paper #]VLD2017-71,CPSY2017-115,RECONF2017-59
Total-ionizing-dose tolerance of an optically reconfigurable gate array

Takumi Fujimori(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2018-01-19
[Paper #]VLD2017-81,CPSY2017-125,RECONF2017-69
FPGAによるデータフロー計算機におけるハードウェア資源割当て最適化

Kohei Nagasu(Tohoku Univ.),  Kentaro Sano(Tohoku Univ.),  

[Date]2018-01-19
[Paper #]VLD2017-85,CPSY2017-129,RECONF2017-73
Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation

Mitsuyoshi Iwatsuji(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  

[Date]2018-01-19
[Paper #]VLD2017-87,CPSY2017-131,RECONF2017-75
Mutant Generation of Performance Tests for LLVM Back-Ends

Kenji Tanaka(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  Masanari Nishimura(Renesas),  Akiya Fukui(Renesas),  

[Date]2018-01-19
[Paper #]VLD2017-88,CPSY2017-132,RECONF2017-76
Accelerating Serialization Protocols for Network-Attached FPGAs

Takuma Iwata(Keio Univ.),  Koya Mitsuzuka(Keio Univ.),  Kohei Nakamura(Keio Univ.),  Yuta Tokusashi(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2018-01-19
[Paper #]VLD2017-84,CPSY2017-128,RECONF2017-72
Accelerating Sequential Learning Algorithm OS-ELM Using FPGA-NIC

Mineto Tsukada(Keio Univ.),  Koya Mitsuzuka(Keio Univ.),  Kohei Nakamura(Keio Univ.),  Yuta Tokusashi(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2018-01-19
[Paper #]VLD2017-83,CPSY2017-127,RECONF2017-71
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