Information and Systems-Reconfigurable Systems(Date:2016/09/05)

Presentation
Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT

Shigeyoshi Watanabe(Shonan Inst. of Tech.),  Tomohiro Yokota(DNP Data Techno),  Shoto Tamai(Oi Electric),  Takumi Sato(Shonan Inst. of Tech.),  

[Date]2016-09-05
[Paper #]RECONF2016-29
[Short Paper] Study and Evaluation of FPGA based I/O Accelerator for the Flash Storage

Kazushi Nakagawa(Hitachi),  Shotaro Shintani(Hitachi),  Hirotoshi Akaike(Hitachi),  Kentaro Shimada(Hitachi),  

[Date]2016-09-05
[Paper #]RECONF2016-26
The effect of the C ++ template meta-programming in high-level synthesis

Kenichiro Mitsuda(ISP),  Owada Hiroshi(ISP),  Shinji Yamamoto(ISP),  

[Date]2016-09-05
[Paper #]RECONF2016-27
細粒度再構成可能デバイスMPLDのIOを考慮したSOMベース配置手法

Tomohiro Tanaka(Hiroshima City Univ),  Kazuya Tanigawa(Hiroshima City Univ),  Tetsuo Hironaka(Hiroshima City Univ),  Takashi Ishiguro(Taiyo Yuden),  

[Date]2016-09-05
[Paper #]RECONF2016-30
JAVAベース高位合成系Synthesijerによる○×ゲーム探索再帰記述のハードウェア化

Yuuya Hiroe(Ritsumeikan Univ.),  Masashi Ono(Ritsumeikan Univ.),  Tomonori Izumi(Ritsumeikan Univ.),  Lin Meng(Ritsumeikan Univ.),  

[Date]2016-09-05
[Paper #]RECONF2016-28
Functional Improvement of cReComp Design Tool for Software-Component Generation of FPGA Processing

Kazushi Yamashina(Utsunomiya Univ.),  Takeshi Ohkawa(Utsunomiya Univ.),  Kanemitsu Ootsu(Utsunomiya Univ.),  Takashi Yokota(Utsunomiya Univ.),  

[Date]2016-09-05
[Paper #]RECONF2016-24
ストリーム画像処理向けパーティクルフィルタのFPGA実装

Akane Tahara(Nagasaki Univ.),  Yoshiki Hayashida(Nagasaki Univ.),  Theint Theint Thu(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  Kiyoshi Oguri(Nagasaki Univ.),  

[Date]2016-09-05
[Paper #]RECONF2016-25
[Invited Talk] Verification and Debugging Support Techniques for High-Level Designs

Takeshi Matsumoto(INCT),  

[Date]2016-09-05
[Paper #]RECONF2016-31
Concept of PC-FPGA Hybrid Cluster system by General-purpose FPGA board

Keisuke Takano(Okayama Univ. of Science),  Akira Uejima(Okayama Univ. of Science),  Ryo Ozaki(Okayama Univ. of Science),  Masaki Kohata(Okayama Univ. of Science),  

[Date]2016-09-06
[Paper #]RECONF2016-33
A Memory-based Accelerator for a Random Forest Classification using Altera SDK for OpenCL

Hiroki Nakahara(TITECH),  Akira Jinguji(TITECH),  Tomoya Fujii(TITECH),  Shinpei Sato(TITECH),  Naoya Maruyama(RIKEN),  

[Date]2016-09-06
[Paper #]RECONF2016-36
A Memory Based Realization of the Binarized Deep Convolutional Neural Network

Hiroki Nakahara(TITECH),  Haruyoshi Yonekawa(TITECH),  Tsutomu Sasao(Meiji Univ.),  Hisashi Iwamoto(Poco a poco Networks),  Masato Motomura(Hokkaido Univ.),  

[Date]2016-09-06
[Paper #]RECONF2016-37
An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation

Daichi Murata(Kobe Univ.),  Tetsuya Hirose(Kobe Univ.),  Nobutaka Kuroki(Kobe Univ.),  Masahiro Numa(Kobe Univ.),  

[Date]2016-09-06
[Paper #]RECONF2016-38
評価関数とパターンマッチングをゲーム木探索に適用したTRAXソルバの実装

Tatsuya Komatsu(Kochi Univ. of Tech.),  Yukio Mitsuyama(Kochi Univ. of Tech.),  

[Date]2016-09-06
[Paper #]RECONF2016-39
A Study of Methodology and Tools for Open-source FPGA Accelerators

Takuya Nakamichi(Kumamoto Univ.),  Qian Zhao(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Date]2016-09-06
[Paper #]RECONF2016-34
[Invited Talk] Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture

Yuki Kobayashi(NEC),  Yoshikazu Watanabe(NEC),  Seiya Shibata(NEC),  Takashi Takenaka(NEC),  Takeo Hosomi(NEC),  Yuichi Nakamura(NEC),  

[Date]2016-09-06
[Paper #]RECONF2016-32
部分再構成によるCPU-FPGA混在クラスタの実現へむけた研究

Yohei Sakamoto(UR),  Kosaku Matsuda(UR),  Shinya Okubo(UR),  Yasunori Osana(UR),  

[Date]2016-09-06
[Paper #]RECONF2016-35