IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2015/06/19)

Presentation

[Special Talk] Semiconductor Innovation seen from Makimoto's Wave and its Impact

Tsugio Makimoto(SSIS),

[Date]2015-06-19
[Paper #]RECONF2015-1

Power optimization of low-power reconfigurable accelerator CMA-SOTB

Koichiro Masuyama(Keio Univ.), Yu Fujita(Keio Univ.), Hayate Okuhara(Keio Univ.), Hideharu Amano(Keio Univ.),

[Date]2015-06-19
[Paper #]RECONF2015-2

High Speed Calculation of Convex Hull in 2D Images using FPGA

Kahori Kemmotsu(Univ. of Tsukuba), Kenji Kanazawa(Univ. of Tsukuba), Yamato Mori(Univ. of Tsukuba), Noriyuki Aibe(SUSUBOX), Moritoshi Yasunaga(Univ. of Tsukuba),

[Date]2015-06-19
[Paper #]RECONF2015-7

ROS compliant componentizing of image processing hardware on a Programmable SoC

Kazushi Yamashina(Utsunomiya Univ.), Takeshi Ohkawa(Utsunomiya Univ.), Kanemitsu Ootsu(Utsunomiya Univ.), Takashi Yokota(Utsunomiya Univ.),

[Date]2015-06-19
[Paper #]RECONF2015-8

Realization of FPGA Control Processing with Functional Safety

Kenichi Morimoto(Nagasaki Univ.), Masanori Nobe(MHPS), Masaharu Tanaka(MHI), Yuichiro Shibata(Nagasaki Univ.), Yudai Shirakura(Nagasaki Univ.), Hidenori Maruta(Nagasaki Univ.), Fujio Kurokawa(Nagasaki Univ.),

[Date]2015-06-19
[Paper #]RECONF2015-10

Evaluation of the third Flex Power FPGA chip in SOTB technology

Masakazu Hioki(AIST), Yasuhiro Ogasahara(AIST), Hanpei Koike(AIST),

[Date]2015-06-19
[Paper #]RECONF2015-3

[Invited Talk] Reliability on Integrated Circuits

Kazutoshi Kobayashi(Kyoto Inst. of Tech.),

[Date]2015-06-19
[Paper #]RECONF2015-13

Consideration of the one-dimensional array processor suitable for a shock tube problem by FPGA

Keisuke Hirofuji(Hiroshima City Univ), Ryo Okuda(Hiroshima City Univ), Kazuya Tanigawa(Hiroshima City Univ), Tetsuo Hironaka(Hiroshima City Univ),

[Date]2015-06-19
[Paper #]RECONF2015-9

Towards the Fastest FPGA-based Sorting Hardware in the World

Ryohei Kobayashi(Tokyo Tech), Kenji Kise(Tokyo Tech),

[Date]2015-06-19
[Paper #]RECONF2015-12

An arithmetic design approach with diversity and redundancy for FPGAs

Yudai Shirakura(Nagasaki Univ.), Kenichi Morimoto(Nagasaki Univ.), Masanori Nobe(MHPS), Masaharu Tanaka(MHI), Yuichiro Shibata(Nagasaki Univ.), Hidenori Maruta(Nagasaki Univ.), Fujio Kurokawa(Nagasaki Univ.),

[Date]2015-06-19
[Paper #]RECONF2015-11

A Classification Hardware with Hierarchical Multiple Scan Window Sizes for Colorectal Endoscopic Diagnosis

Takumi Okamoto(Hiroshima Univ.), Tetsushi Koide(Hiroshima Univ.), Tatsuya Shimizu(Hiroshima Univ.), Koki Sugi(Hiroshima Univ.), Anh-Tuan Hoang(Hiroshima Univ.), Hikaru Satoh(Hiroshima Univ.), Toru Tamaki(Hiroshima Univ.), Bisser Raytchev(Hiroshima Univ.), Kazufumi Kaneda(Hiroshima Univ.), Shigeto Yoshida(Hiroshima General Hospital of West Japan Railway Company), Hiroshi Mieno(Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka(Hiroshima Univ.),

[Date]2015-06-19
[Paper #]RECONF2015-5

Consideration for Visual Word Feature Transformation Hardware based on Bag-of-Features

Koki Sugi(Hiroshima Univ.), Tetsushi Koide(Hiroshima Univ.), Tatsuya Shimizu(Hiroshima Univ.), Takumi Okamoto(Hiroshima Univ.), Anh-Tuan Hoang(Hiroshima Univ.), Hikaru Satoh(Hiroshima Univ.), Toru Tamaki(Hiroshima Univ.), Bisser Raytchev(Hiroshima Univ.), Kazufumi Kaneda(Hiroshima Univ.), Shigeto Yoshida(Hiroshima General Hospital of West Japan Railway Company), Hiroshi Mieno(Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka(Hiroshima Univ.),

[Date]2015-06-19
[Paper #]RECONF2015-6

An Area Optimization of 3D FPGA with high speed inter-layer communication link

Yuto Takeuchi(Kumamoto Univ), Qian Zhao(Kumamoto Univ), Motoki Amagasaki(Kumamoto Univ), Masahiro Iida(Kumamoto Univ), Morihiro Kuga(Kumamoto Univ), Toshinori Sueyoshi(Kumamoto Univ),

[Date]2015-06-19
[Paper #]RECONF2015-4

A Deep Convolutional Neural Network Based on Nested Residue Number System

Hiroki Nakahara(Ehime Univ.), Tsutomu Sasao(Meiji Univ.),

[Date]2015-06-20
[Paper #]RECONF2015-17

An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device

Tieyuan Pan(Waseda Univ.), Zhu Li(Waseda Univ.), Lian Zeng(Waseda Univ.), Takahiro Watanabe(Waseda Univ.), Yasuhiro Takashima(Univ. of Kitakyushu),

[Date]2015-06-20
[Paper #]RECONF2015-26

FPGA design using high-level description

Fang-Xiang Gao(Univ. Tsukuba), Yoshiki Yamaguchi(Univ. Tsukuba), Yuetsu Kodama(Univ. Tsukuba),

[Date]2015-06-20
[Paper #]RECONF2015-31

Real Chip evaluation of a dynamically reconfigurable processor MuCCRA-4 with ST micro 28nm Process

Hideharu Amano(Keio Univ.), Toru Katagiri(Keio Univ.),

[Date]2015-06-20
[Paper #]RECONF2015-21

A Rapid Verification Environment for Statistical Evaluation of PUF Circuits

Toshihiro Katashita(AIST), Yasunori Onda(AIST), Yohei Hori(AIST),

[Date]2015-06-20
[Paper #]RECONF2015-18

Consideration of a reconfigurable device MPLD constructed with MLUTs that equips a crossbar switch

Naoya Tokusada(HCU), Tetsuo Hironaka(HCU), Kazuya Tanigawa(HCU), Takashi Ishiguro(Taiyo Yuden),

[Date]2015-06-20
[Paper #]RECONF2015-25

A SW/HW Interface Implementation Method in the System Design Environment for Programmable SoCs

Yusuke Tani(Kyoto Univ.), Takuya Hatayama(Kyoto Univ.), Hideki Takase(Kyoto Univ.), Kazuyoshi Takagi(Kyoto Univ.), Naofumi Takagi(Kyoto Univ.),

[Date]2015-06-20
[Paper #]RECONF2015-14