Information and Systems-Reconfigurable Systems(Date:2015/01/22)

Presentation
表紙

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[Date]2015/1/22
[Paper #]
目次

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[Date]2015/1/22
[Paper #]
Performance Acceleration of Document-Oriented Stores Using GPUs

Shin MORISHIMA,  Hiroki MATSUTANI,  

[Date]2015/1/22
[Paper #]VLD2014-113,CPSY2014-122,RECONF2014-46
Accelerating NOSQLs using FPGA NIC and In-Kernel Key-Value Cache

Korechika TAMURA,  Ami HAYASHI,  Yuta TOKUSASHI,  Hiroki MATSUTANI,  

[Date]2015/1/22
[Paper #]VLD2014-114,CPSY2014-123,RECONF2014-47
An Online Outlier Detector for FPGA NICs

Ami HAYASHI,  Yuta TOKUSASHI,  Hiroki MATSUTANI,  

[Date]2015/1/22
[Paper #]VLD2014-115,CPSY2014-124,RECONF2014-48
Turbo Boost Router : An On-Chip Router Supporting Deterministic and Adaptive Routings

Natsuki HOMMA,  Go MATSUMURA,  Michihiro KOIBUCHI,  Hediharu AMANO,  Hiroki MATSUTANI,  

[Date]2015/1/22
[Paper #]VLD2014-116,CPSY2014-125,RECONF2014-49
NoC Architecture with Priority-based Packet Overtaking and Resource Control

Shuhei OTSUKI,  Keigo MIZOTANI,  Masayoshi TAKASU,  Daiki YAMAZAKI,  Nobuyuki YAMASAKI,  

[Date]2015/1/22
[Paper #]VLD2014-117,CPSY2014-126,RECONF2014-50
Radiation tolerance of parallel configuration of optically reconfigurable gate arrays

Hiroyuki ITO,  Retsu MORIWAKI,  Minoru WATANABE,  

[Date]2015/1/22
[Paper #]VLD2014-118,CPSY2014-127,RECONF2014-51
Circuit Design and Valuation of Reconfigurable Logic Circuit

Junki Kato,  Shigeyoshi Watanabe,  Hiroshi Ninomiya,  Manabu Kobayashi,  Yasuyuki Miura,  

[Date]2015/1/22
[Paper #]VLD2014-119,CPSY2014-128,RECONF2014-52
Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections

Qian ZHAO,  Motoki AMAGASAKI,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2015/1/22
[Paper #]VLD2014-120,CPSY2014-129,RECONF2014-53
Human Friendly Robot Based on Ontologies

Takahira YAMAGUCHI,  

[Date]2015/1/22
[Paper #]VLD2014-121,CPSY2014-130,RECONF2014-54
A High-Speed parallel Logic Simulation Method Using Multi-core Processor

YUYA TAKEUCHI,  MASAHIKO TOYONAGA,  MICHIAKI MURAOKA,  

[Date]2015/1/22
[Paper #]Vol.2015-SLDM-169 No.10
A High Speed Logic Simulation Engine using FPGA

Natsuki Matsumoto,  Michiaki Muraoka,  

[Date]2015/1/22
[Paper #]Vol.2015-SLDM-169 No.11
A High-Speed Parallel Logic Simulater Using GP-GPU

Takuya Hashiguchi,  Toyonaga Masahiko /,  Michiaki Muraoka,  

[Date]2015/1/22
[Paper #]Vol.2015-SLDM-169 No.12
An AWF Digital Spectrometer for a Radio Telescope

Hiroki NAKAHARA,  Hiroyuki NAKANISHI,  Kazumasa IWAI,  

[Date]2015/1/22
[Paper #]VLD2014-122,CPSY2014-131,RECONF2014-55
Small Bandwidth Compression Hardware Exploited Distribution of Length of Prediction Residual

Tomohiro Ueno,  Ryo Ito,  Kentaro Sano,  Satoru Yamamoto,  

[Date]2015/1/22
[Paper #]VLD2014-123,CPSY2014-132,RECONF2014-56
Inter-Cube Data-Exchanging for Custom Fluid Computing Machine Based on Building-Cube Method

Tomoya UENO,  Tomohiro UENO,  Kentaro SANO,  Satoru YAMAMOTO,  

[Date]2015/1/22
[Paper #]VLD2014-124,CPSY2014-133,RECONF2014-57
FPGA Implementation of a High Time Resolution Signal Generation Circuit for PWM

Shun KASHIWAGI,  Daiki MITSUTAKE,  Hironobu TANIGUCHI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  Hidenori MARUTA,  Fujio KUROKAWA,  

[Date]2015/1/22
[Paper #]VLD2014-125,CPSY2014-134,RECONF2014-58
Study on Clock Tree Delay Analysis Mechanism

Goro Suzuki,  Ryutaro Takeda,  

[Date]2015/1/22
[Paper #]VLD2014-126,CPSY2014-135,RECONF2014-59
Temperature sensor applying Body Bias in Silicon-on-Thin-BOX

Tsubasa KOSAKA,  Shohei NAKAMURA,  Kimiyoshi USAMI,  

[Date]2015/1/22
[Paper #]VLD2014-127,CPSY2014-136,RECONF2014-60
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