IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2014/09/11)

Presentation

[Date]2014/9/11
[Paper #]

Architecture Development for the Real-time Computer-Aided Diagnosis of Colorectal Endoscopic Images with NBI Magnification

Tetsushi KOIDE,

[Date]2014/9/11
[Paper #]RECONF2014-17

Prototype of fault tolerant FPGA using 65nm CMOS process

Motoki AMAGASAKI, Takuya KAJIWARA, Kentaro FUJISAWA, Qian ZHAO, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI,

[Date]2014/9/11
[Paper #]RECONF2014-18

A study of run-time fault detection mechanism for fault-tolerant FPGAs

Kentaro FUJISAWA, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI,

[Date]2014/9/11
[Paper #]RECONF2014-19

Radiation tolerance of a holographic memory part on an optically reconfigurable gate array

Retsu MORIWAKI, Hiroyuki ITO, Akira MAEKAWA, Minoru WATANABE, Akifumi OGIWARA,

[Date]2014/9/11
[Paper #]RECONF2014-20

Challenge for Ultrafast 10K-Node NoC emulation on FPGA

CHU Thiem VAN, Shimpei SATO, Kenji KISE,

[Date]2014/9/11
[Paper #]RECONF2014-21

Dynamically reconfigurable protocol-processing hardware for communications SoC

Saki HATTA, Nobuyuki TANAKA, Satoshi SHIGEMATSU,

[Date]2014/9/11
[Paper #]RECONF2014-22

A Time-division Multiplexing Method of Inter-FPGA Signals for Multi-FPGA Systems with Various Topologies

Masato INAGI, Yuichi NAKAMURA, Yasuhiro TAKASHIMA, Shin'ichi WAKABAYASHI,

[Date]2014/9/11
[Paper #]RECONF2014-23

On The Second Flex Power FPGA chip with SOTB transistors

Hanpei KOIKE, Chao MA, Masakazu HIOKI, Yasuhiro OGASAHARA, Toshiyuki TSUTSUMI, Tadashi NAKAGAWA, Toshihiro SEKIGAWA,

[Date]2014/9/11
[Paper #]RECONF2014-24

Parallel-operation-oriented optically reconfigurable gate array

Takumi FUJIMORI, Minoru WATANABE,

[Date]2014/9/11
[Paper #]RECONF2014-25

Research & Development of FPGA Applications in A Company

Takefumi MIYOSHI,

[Date]2014/9/11
[Paper #]RECONF2014-26

Building a Mixed Software Hardware Pipeline on a CPU-FPGA platform

Takaaki MIYAJIMA, David THOMAS, Hideharu AMANO,

[Date]2014/9/11
[Paper #]RECONF2014-27

Evaluation and Implementation of the Calculation Feature to PEACH2

Takuya KUHARA, Takaaki MIYAJIMA, Toshihiro HANAWA, Hideharu AMANO,

[Date]2014/9/11
[Paper #]RECONF2014-28

GRAPE9-MPX: A development of an accelerator dedicated for arbitrary-precision arithmetic by the FPGA boards

Shinji MOTOKI, Hiroshi DAISAKA, Naohito NAKASATO, Tadashi ISHIKAWA, Fukuko YUASA, Toshiyuki FUKUSHIGE, Atsushi KAWAI, Jun'ichiro MAKINO,

[Date]2014/9/11
[Paper #]RECONF2014-29

Discussion for speed up of three-dimensional space imaging using sound Waves

Keiko ODA, Akira KOJIMA, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2014/9/11
[Paper #]RECONF2014-30

FPGA Implementation of a Compact Processor Yukiyama for Tiny SoC

Yuichi WATANABE, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2014/9/11
[Paper #]RECONF2014-31

A Trial Hardware Design of a Recursive Function to Solve "OX game" by Code-Modification and High-Level Synthesis

Masashi Ohno, Yu Nakahara, Tomonori Izum, Meng Lin,

[Date]2014/9/11
[Paper #]RECONF2014-32

Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic

Shunji NISHIMURA, Motoki AMAGASAKI, Toshinori SUEYOSHI,

[Date]2014/9/11
[Paper #]RECONF2014-33

複写される方へ

[Date]2014/9/11
[Paper #]