IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2014/06/04)

Presentation

表紙

[Date]2014/6/4
[Paper #]

Prospects of Custom Accelerators for Large-Scale Computation : Perspectives of Applications, Architectures and Circuits

Masanori HARIYAMA,

[Date]2014/6/4
[Paper #]RECONF2014-1

A Dynamic Reconfigurable Mixed Analog-Digital Filter Applied to an Acoustic Diagnostic

Hiroki NAKAHARA, Hideki YOSHIDA, Tsutomu SASAO, Renji MIKAMI,

[Date]2014/6/4
[Paper #]RECONF2014-2

Optimized HOG for Database System

Mao HATTO, Takaaki MIYAJIMA, Hiroki MATSUTANI, Hideharu AMANO,

[Date]2014/6/4
[Paper #]RECONF2014-3

Highly-Parallel FPGA Accelerator for DNA Sequence Alignment Using the Burrows-Wheeler Algorithm

Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA,

[Date]2014/6/4
[Paper #]RECONF2014-4

Improvement of Implementability by Exploring Routing Architecture in Flex Power FPGA

Masakazu HIOKI, Toshihiro SEKIGAWA, Tadashi NAKAGAWA, Yasuhiro OGASAHARA, Toshiyuki TSUTSUMI, Hanpei KOIKE,

[Date]2014/6/4
[Paper #]RECONF2014-5

An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture

Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA,

[Date]2014/6/4
[Paper #]RECONF2014-6

Three-dimensional FPGA Structure using High-speed Serial Communication

Takuya KAJIWARA, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI,

[Date]2014/6/4
[Paper #]RECONF2014-7

Body bias control of low-power reconfigurable accelerator CMA-SOTB

Yu FUJITA, KORYO So, Hideharu AMANO,

[Date]2014/6/4
[Paper #]RECONF2014-8

A Design of Blokus Player Algorithm with Impulse High-Level Synthesis Tools

Ryo KAWAI, Tomonori IZUMI,

[Date]2014/6/4
[Paper #]RECONF2014-9

Zyndroid : HW/SW Coprocessing Platform for Android Applications

Susumu MASHIMO, Morihiro KUGA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI,

[Date]2014/6/4
[Paper #]RECONF2014-10

A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis

Koji OKINA, Rie SOEJIMA, Keisuke DOHI, Yuichiro SHIBATA, Kiyoshi OGURI,

[Date]2014/6/4
[Paper #]RECONF2014-11

A Study on Accelerating Image Recognition Processing by HW/SW Cooperative Processing on an FPGA for Automatic Watch System on Navigation

Takeshi OHKAWA, Yohei MATSUMOTO, Daichi UETAKE, Kanemitsu OOTSU, Takashi YOKOTA,

[Date]2014/6/4
[Paper #]RECONF2014-12

Implementation of a RISC Processor with a Complex Instruction Accelerator : Return to a CISC

Ryota SUZUKI, Takefumi MIYOSHI, Hironori NAKAJO,

[Date]2014/6/4
[Paper #]RECONF2014-13

FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Set Associative Cache

Kenji KANAZAWA, Tsutomu MARUYAMA,

[Date]2014/6/4
[Paper #]RECONF2014-14

Design of an FPGA-Based Accelerator for Shortest-Path Search over Large-Scale Graphs

Yasuhiro TAKEI, Masanori HARIYAMA, Michitaka KAMEYAMA,

[Date]2014/6/4
[Paper #]RECONF2014-15

SIMD可変構造プロセッサにおけるエネルギー対性能の評価(アプリケーション高速化)

[Date]2014/6/4
[Paper #]RECONF2014-16

複写される方へ

[Date]2014/6/4
[Paper #]

Notice for Photocopying

[Date]2014/6/4
[Paper #]