Information and Systems-Reconfigurable Systems(Date:2011/09/19)

Presentation
表紙

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[Date]2011/9/19
[Paper #]
目次

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[Date]2011/9/19
[Paper #]
低電力アクセラレータCMA-1におけるウェーブパイプラインの適用(デバイスアーキテクチャ)

Nobuaki OZAKI,  Yoshihiro YASUDA,  Yoshiki SAITOU,  Daisuke IKEBUCHI,  Masayuki KIMURA,  Hideharu AMANO,  Hiroshi NAKAMURA,  Kimiyoshi USAMI,  Mitaro NAMIKI,  Masaaki KONDO,  

[Date]2011/9/19
[Paper #]RECONF2011-22
Feasibility study of Nonvolatile Reconfigurable Device by using a Standerd CMOS logic process

Shuji KUNIMITSU,  Mamoru TERAUCHI,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  Masayuki SATO,  Takashi ISHIGURO,  

[Date]2011/9/19
[Paper #]RECONF2011-23
Low Power Dynamically Reconfigurable Processor with Dual-Vdd/Dual-Vth and tis Optimization

Kazuei HIRONAKA,  Hideharu AMANO,  

[Date]2011/9/19
[Paper #]RECONF2011-24
A Novel Cluster Structure based on Input Sharing of LUTs

Toshiya TAKAHASHI,  Kazuki INOUE,  Motoki AMAGASAKI,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2011/9/19
[Paper #]RECONF2011-25
FPGA placement based on Self-Organized Map

Yasuaki TOMONARI,  Motoki AMAGASAKI,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2011/9/19
[Paper #]RECONF2011-26
Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram

Daiki KANO,  Ryota YAMAZAKI,  Naohiko SHIMIZU,  

[Date]2011/9/19
[Paper #]RECONF2011-27
Evaluation of Reconfigurable Computer System using Application of Parliamentary System

Takahiro KAJIYAMA,  Akira KOJIMA,  Tetsuo HIRONAKA,  

[Date]2011/9/19
[Paper #]RECONF2011-28
Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs : Hardware and Reconfiguration Layers

Krzysztof Jozwik,  Shinya Honda,  Hiroyuki Tomiyama,  Hiroaki Takada,  

[Date]2011/9/19
[Paper #]RECONF2011-29
Relocation of Partial Reconfiguration Data for Dynamic Reconfigurable System

Sadaki USAGAWA,  Yoshinori ICHINOIYA,  Motoki AMAGASAKI,  Morihiro KUGA,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2011/9/19
[Paper #]RECONF2011-30
Dependability of Automotive Embedded Systems(Invited Talk)

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[Date]2011/9/19
[Paper #]RECONF2011-31
Case Studies on an FPGA with System-Level Multiprocessor Design Toolset

Seiya SHIBATA,  Yuki ANDO,  Shinya HONDA,  Hiroyuki TOMIYAMA,  Hiroaki TAKADA,  

[Date]2011/9/19
[Paper #]RECONF2011-32
A Design Framework for relieving a HW Bottleneck on FPGAs Connected with a High-Speed Data Bus

Koichi ARAKI,  Yukinori SATO,  Yasushi IGUCHI,  

[Date]2011/9/19
[Paper #]RECONF2011-33
A Basic Implementation of LUT-based Dynamic and Partial Reconfiguration from Remote site

Hiroyuki KAWAI,  Moritoshi YASUNAGA,  

[Date]2011/9/19
[Paper #]RECONF2011-34
Parallel template matching operations on a dynamically reconfigurable vision-chip architecture

Yuichiro YAMAJI,  Hironari NAKADA,  Minoru WATANABE,  Shoji KAWAHITO,  

[Date]2011/9/19
[Paper #]RECONF2011-35
Performance Evaluation of Power Monitoring Programs on Reconfigurable Processor DS-HIE

Kyohei TAO,  Takatoshi TAMAOKI,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2011/9/19
[Paper #]RECONF2011-36
A Proposal of Pattern Matching Techniques using Dynamically Reconfigurable Hardware

Masato NOGAMI,  Nobuya WATANABE,  Akira NAGOYA,  

[Date]2011/9/19
[Paper #]RECONF2011-37
Design and Implementation of Adaptive Viterbi Decoder Using Dynamic Reconfigurable System STP Engine

Yuken KISHIMOTO,  Takao TOI,  Takaaki MIYAJIMA,  Hideharu AMANO,  

[Date]2011/9/19
[Paper #]RECONF2011-38
Performance Comparison of the Pattern-Recognition Hardware Using Data-Direct-Implementation Approach

Yusuke SATO,  Moritoshi YASUNAGA,  Noriyuki AIBE,  

[Date]2011/9/19
[Paper #]RECONF2011-39
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