Information and Systems-Reconfigurable Systems(Date:2011/01/10)

Presentation
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[Date]2011/1/10
[Paper #]
目次

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[Date]2011/1/10
[Paper #]
UMLアクティビティ図のハードウェア記述言語NSLへの動作合成(コンピュータシステム,FPGA応用及び一般)

Toshihiro KAMIKAGE,  Ryota YAMAZAKI,  Naohiko SHIMIZU,  

[Date]2011/1/10
[Paper #]VLD2010-84,CPSY2010-39,RECONF2010-53
Implementation and evaluation of program development middleware for Cell Broadband Engine clusters

Toshiaki KAMATA,  Akihiro SHITARA,  Yuri NISHIKAWA,  Masato YOSHIMI,  Hideharu AMANO,  

[Date]2011/1/10
[Paper #]VLD2010-85,CPSY2010-40,RECONF2010-54
Proposal and Preliminary Evaluation of System Diagnosis Technique for Large-scale Computer Network by Using Bayesian Network

Shingo HARASHIMA,  Hitoshi YABUSAKI,  Wataru SAKAMOTO,  Hiroaki NISHI,  

[Date]2011/1/10
[Paper #]VLD2010-86,CPSY2010-41,RECONF2010-55
Implementation of Energy Management Sensor Network and Application to Home Envirnment

Yukio SUHARA,  Tomohisa NAKABE,  Hiroaki NISHI,  

[Date]2011/1/10
[Paper #]VLD2010-87,CPSY2010-42,RECONF2010-56
Highly efficient mapping of electromagnetic wave interactions using the FDTD method for antenna designing on a CUDA-compatible GPU

Keisuke DOHI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  Takafumi FUJIMOTO,  

[Date]2011/1/10
[Paper #]VLD2010-88,CPSY2010-43,RECONF2010-57
Parallelization of the channel width search for FPGA routing

Hiroomi SAWADA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2011/1/10
[Paper #]VLD2010-89,CPSY2010-44,RECONF2010-58
Approximated Variable Scheduling for High-Level Synthesis

Kousuke SONE,  Nagisa ISHIURA,  

[Date]2011/1/10
[Paper #]VLD2010-90,CPSY2010-45,RECONF2010-59
A Heuristic Method using CODCs for Extraction of Maximum Observability Don't Care Set

Taiga TAKATA,  Yusuke MATSUNAGA,  

[Date]2011/1/10
[Paper #]VLD2010-91,CPSY2010-46,RECONF2010-60
Power reduction in Dynamically Reconfigurable Processor by Dynamically V_
Switching and a mapping technique to reduce energy overhead

Tatsuya Yamamoto,  Kazuei Hironaka,  Yuki Hayakawa,  Masayuki Kimura,  Hideharu Amano,  Kimiyoshi Usami,  

[Date]2011/1/10
[Paper #]VLD2010-92,CPSY2010-47,RECONF2010-61
AllianceVHDLツールセットによるROHM0.18μmチップ試作検証 : 配置配線検証ツールの試行(VLSI設計技術,FPGA応用及び一般)

Tatsuya HOSOKAWA,  Hiroshi IMAI,  Naohiko SHIMIZU,  

[Date]2011/1/10
[Paper #]VLD2010-93,CPSY2010-48,RECONF2010-62
Acceleration of Regression Test of Compilers by Program Merging

Kazushi MORIMOTO,  Nagisa ISHIURA,  Yuki UCHIYAMA,  Nobuyuki HIKICHI,  

[Date]2011/1/10
[Paper #]VLD2010-94,CPSY2010-49,RECONF2010-63
Automatic Retargeting of Binutils and GDB Based on Plug-in Method

Soichiro TAGA,  Takahiro KUMURA,  Nagisa ISHIURA,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2011/1/10
[Paper #]VLD2010-95,CPSY2010-50,RECONF2010-64
Residue Arithmetic and FIR Filter Design Based on Minimal Signed-Digit Number Representation

Rui CHEN,  Yuuki TANAKA,  Shugang WEI,  

[Date]2011/1/10
[Paper #]VLD2010-96,CPSY2010-51,RECONF2010-65
Audio dynamic range compression using polynomial equations

Tatsuya MIYASHITA,  Kazuhiro MOTEGI,  Shugang WEI,  

[Date]2011/1/10
[Paper #]VLD2010-97,CPSY2010-52,RECONF2010-66
A Regular Expression Matching Circuit Based on a Decomposed Automaton

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2011/1/10
[Paper #]VLD2010-98,CPSY2010-53,RECONF2010-67
Encoding Methods of Multiple Data Streams for Hardware Compressors of Floating-Point Data

Kentaro SANO,  Kazuya KATAHIRA,  Satoru YAMAMOTO,  

[Date]2011/1/10
[Paper #]VLD2010-99,CPSY2010-54,RECONF2010-68
FPGA implementation of human detectin with HOG features and AdaBoost

Kazuhiro NEGI,  Keisuke DOHI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2011/1/10
[Paper #]VLD2010-100,CPSY2010-55,RECONF2010-69
A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems

Tomonori IZUMI,  

[Date]2011/1/10
[Paper #]VLD2010-101,CPSY2010-56,RECONF2010-70
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