Information and Systems-Reconfigurable Systems(Date:2009/05/07)

Presentation
表紙

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[Date]2009/5/7
[Paper #]
目次

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[Date]2009/5/7
[Paper #]
Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension

Ken'ichi UMEDA,  Takuro UCHIDA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2009/5/7
[Paper #]RECONF2009-1
Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3

Yoshihiro YASUDA,  Yoshiki SAITO,  Toru SANO,  Masaru KATO,  Hideharu AMANO,  

[Date]2009/5/7
[Paper #]RECONF2009-2
Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs

Sen IN,  Hiroki MATSUTANI,  Daihan WANG,  Michihiro KOIBUCHI,  Hideharu AMANO,  

[Date]2009/5/7
[Paper #]RECONF2009-3
A Power of FPGA Redection Using FPGA Routing Structure Based on the Small-world Network

Shoichi NISHIDA,  Yuzo NISHIOKA,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2009/5/7
[Paper #]RECONF2009-4
Proposal and Implementation of High Throughput Algorithm for Combination Generation

Akira TSUJI,  Norio YAMAGAKI,  Satoshi KAMIYA,  

[Date]2009/5/7
[Paper #]RECONF2009-5
Accelerating HMMER search using FPGA

Toyokazu TAKAGI,  Tutomu MARUYAMA,  

[Date]2009/5/7
[Paper #]RECONF2009-6
Performance evaluation of an auto-generation algorithm of hardware modules for an FPGA-based general-purpose biochemical simulator

Tomonori OOYA,  Hideki YAMADA,  Tomoya ISHIMORI,  Yuichiro SHIBATA,  Yasunori OSANA,  Masato YOSHIMI,  Yuri NISHIKAWA,  Hideharu AMANO,  Akira FUNAHASHI,  Noriko HIROI,  Kiyoshi OGURI,  

[Date]2009/5/7
[Paper #]RECONF2009-7
Development of Interactive Supercomputing Environment

Shinichiro MORI,  Tomohiro KURODA,  Naoto KUME,  Yoshihiro KURODA,  Megumi NAKAO,  Hajime Shimada,  Yasuhiko NAKASHIMA,  Shinji TOMITA,  

[Date]2009/5/7
[Paper #]RECONF2009-8
Recovery and syncronization technique for TMR softcore processor

Yoshihiro ICHINOMIYA,  Shiro TANOUE,  Toshio YABUTA,  Motoki AMAGASAKI,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2009/5/7
[Paper #]RECONF2009-9
A low-power clustering tool using both routability and activity for FPGAs

Junya ETO,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2009/5/7
[Paper #]RECONF2009-10
A Memory Access Optimization Method for Reconfigurable Systems Based on a Multithread Programming Model

Keisuke DOHI,  Sayaka SHIDA,  Yuichiro SHIBATA,  Tsuyoshi HAMADA,  Tomonari MASADA,  Kiyoshi OGURI,  

[Date]2009/5/7
[Paper #]RECONF2009-11
Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis

Yohei HORI,  Mai ITOH,  Hideki IMAI,  

[Date]2009/5/7
[Paper #]RECONF2009-12
Evaluation of a High-speed Classification System using Dynamic and Partial Reconfiguration

Hiroyuki KAWAI,  Yoshiki YAMAGUCHI,  Moritoshi YASUNAGA,  

[Date]2009/5/7
[Paper #]RECONF2009-13
Real-time processing of local contrast enhancement on FPGA

Kentaro KOKUFUTA,  Tsutomu MARUYAMA,  

[Date]2009/5/7
[Paper #]RECONF2009-14
Performance comparison of GPU and FPGA in image processing

Shuichi ASANO,  Tutomu MARUYAMA,  

[Date]2009/5/7
[Paper #]RECONF2009-15
A comparative study of implementing N-body simulation on FPGAs, GPUs and general purpose processors

Tsuyoshi Hamada,  Khaled Benkrid,  Keigo Nitadori,  Yuichiro Shibata,  Kiyoshi Oguri,  

[Date]2009/5/7
[Paper #]RECONF2009-16
Modularizing Flux Limiter Functions in UPACS for CFD Accelerator FLOPS-2D

Kenta INAKAGATA,  Hirokazu MORISHITA,  Yasunori OSANA,  Naoyuki FUJITA,  Hideharu AMANO,  

[Date]2009/5/7
[Paper #]RECONF2009-17
Acceleration of UPACS subroutines with FPGAs

Takaaki YOKOYAMA,  Hirokazu MORISHITA,  Yasunori OSANA,  Naoyuki FUJITA,  Hideharu AMANO,  

[Date]2009/5/7
[Paper #]RECONF2009-18
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