Information and Systems-Reconfigurable Systems(Date:2008/11/10)

Presentation
表紙

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[Date]2008/11/10
[Paper #]
目次

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[Date]2008/11/10
[Paper #]
An emulation experiment of an inversion/non-inversion dynamic optical reconfiguration architecture

Shinichi KATO,  Minoru WATANABE,  

[Date]2008/11/10
[Paper #]RECONF2008-38
Assembly accuracy of a holographic memory in an optically reconfigurable gate array

HIRONOBU Morita,  Minoru WATANABE,  

[Date]2008/11/10
[Paper #]RECONF2008-39
Preliminary Evaluations of SMA : A Massive Array of Low-Power Reconfigurable Processors

Hideharu AMANO,  Kyundong KIM,  Hiroki MATSUTANI,  Tunbunheng VASUTAN,  Yoshihiro YASUDA,  Masaaki KONDO,  Hiroshi NAKAMURA,  Kimiyoshi USAMI,  

[Date]2008/11/10
[Paper #]RECONF2008-40
A Method of Processing Data-Parallel Tasks on Multi-Context Reconfigurable Processor

Koichi ARAKI,  Yukinori SATO,  Yasushi INOGUCHI,  

[Date]2008/11/10
[Paper #]RECONF2008-41
A Study of Local Interconnect Architecture for Variable Grain Logic Cell

Kazuki INOUE,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2008/11/10
[Paper #]RECONF2008-42
Adaptive routing of the 2-D torus network based on a Turn model

Kazuya Matoyama,  Yasuyuki Miura,  Shigeyoshi Watanabe,  

[Date]2008/11/10
[Paper #]RECONF2008-43
Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network

Masahiro Kaneko,  Yasuyuki Miura,  Shigeyoshi Watanabe,  

[Date]2008/11/10
[Paper #]RECONF2008-44
Soft Error Mitigation Techniques for FPGA Switch Matrices

Yuki KOU,  Masaki NAKANISHI,  Shigeru YAMASHITA,  Yasuhiko NAKASHIMA,  

[Date]2008/11/10
[Paper #]RECONF2008-45
Inter-FPGA communication mechanism of FPGA-array for high-performance difference scheme computation

LUZHOU WANG,  Kentaro SANO,  Yoshiaki HATSUDA,  Satoru YAMAMOTO,  

[Date]2008/11/10
[Paper #]RECONF2008-46
The End of Moore's Law and the Future of Computing Systems, Probably

Krishna V. PALEM,  

[Date]2008/11/10
[Paper #]RECONF2008-47
C-based Programmable-HW Core "STP Engine": Current Status and the Future

Masato Motomura,  

[Date]2008/11/10
[Paper #]RECONF2008-48
On Programmable Two-Variable Numerical Function Generators

Shinobu NAGAYAMA,  Tsutomu SASAO,  Jon T. BUTLER,  

[Date]2008/11/10
[Paper #]RECONF2008-49
An Adaptive Pattern Recognition hardware with On-chip Dynamic and Partial Reconfiguration

H. KAWAI,  Y. YAMAGUCHI,  M. YASUNAGA,  K. GLETTE,  J. TORESSEN,  

[Date]2008/11/10
[Paper #]RECONF2008-50
A Novel Network Optimization Method using On-Chip Virtual Network on Dynamically Reconfigurable Processor DAPDNA-2

Shan GAO,  Taku KIHARA,  Sho SHIMIZU,  Yutaka ARAKAWA,  SHIBA Kosuke /,  

[Date]2008/11/10
[Paper #]RECONF2008-51
An improvement of Black-Diamond compiler for representing target dynamically reconfigurable architecture

Vasutan TUNBUNHENG,  Hideharu AMANO,  

[Date]2008/11/10
[Paper #]RECONF2008-52
The Experiment of Automatic circuit generation for image processing using extended C code on DRP : DFC, the Language of Hardware generation for DAPDNA-its issue and solution

Kazuo YAMADA,  Takao NAITO,  Mitsumasa YOSHIMURA,  Jiro IWAI,  

[Date]2008/11/10
[Paper #]RECONF2008-53
Development of Side-channel Attack Standard Evaluation BOard and Tool

Yohei HORI,  Toshihiro KATASHITA,  Hirofumi SAKANE,  Akashi SATOH,  Kenji TODA,  Hideki IMAI,  

[Date]2008/11/10
[Paper #]RECONF2008-54
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[Date]2008/11/10
[Paper #]
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