Information and Systems-Reconfigurable Systems(Date:2008/09/18)

Presentation
表紙

,  

[Date]2008/9/18
[Paper #]
目次

,  

[Date]2008/9/18
[Paper #]
Acceleration of two-dimensional liquid simulation using FPGAs

Anna SATO,  Yuichi OKUYAMA,  Tsuyoshi HAMADA,  Junji KITAMICHI,  Kenichi KURODA,  

[Date]2008/9/18
[Paper #]RECONF2008-23
Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation

Naomichi FURUSHIMA,  Nobuya WATANABE,  Akira NAGOYA,  

[Date]2008/9/18
[Paper #]RECONF2008-24
An implementation of road sign recognition algorithm using levenshtein distance on FPGA

Souichi SHIMIZU,  Yoshiaki AJIOKA,  Masatoshi ARAI,  Daisuke KONNO,  Tomomichi NANBA,  Hideharu AMANO,  

[Date]2008/9/18
[Paper #]RECONF2008-25
An automatic combine algorithm of arithmetic pipelines for an FPGA-based biochemical simulator focused on similarities of rate law functions

Hideki YAMADA,  Tomoya ISIMORI,  Yuichiro SHIBATA,  Yasunori OSANA,  Masato YOSHIMI,  Yuri NISHIKAWA,  Hideharu AMANO,  Akira FUNAHASHI,  Noriko HIROI,  Kiyoshi OGURI,  

[Date]2008/9/18
[Paper #]RECONF2008-26
A Proposal of the Network Switch for a PC cluster that can change connection of Distributed Shared Memory

Yoshimasa OHNISHI,  Takaichi YOSHIDA,  

[Date]2008/9/18
[Paper #]RECONF2008-27
A Hardware Evaluation System for 2D Interconnection Networks by using an FPGA Based Network Card

Akira UEJIMA,  Masaki KOHATA,  

[Date]2008/9/18
[Paper #]RECONF2008-28
An Implementation of Operating System Functions for a Distributed FPGA Cluster System

Akira KOJIMA,  Kazuya TOKUNAGA,  Tetsuo HIRONAKA,  

[Date]2008/9/18
[Paper #]RECONF2008-29
Operating System and Reconfigurable Hardware

Hideo TANIGUCHI,  

[Date]2008/9/18
[Paper #]RECONF2008-30
A measurement of retention time of a dynamic optically reconfigurable gate array with large gates

Daisaku SETO,  Minoru WATANABE,  

[Date]2008/9/18
[Paper #]RECONF2008-31
Development of Digit-serial Floating Point Units for Scientific Computation Engine

Taiga BAN,  Yuu SHIRAISHI,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2008/9/18
[Paper #]RECONF2008-32
Exploration of Input Granularity Optimization for Variable Grain Logic Cell

Masahiro KOGA,  Hiroshi MIURA,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2008/9/18
[Paper #]RECONF2008-33
Practice Evaluation of Dynamically Reconfigurable Processor MuCCRA-2β

Yoshiki SAITO,  Masaru KATO,  Shotaro SAITO,  Toru SANO,  Keiichiro HIRAI,  Takashi NISHIMURA,  Takuro NAKAMURA,  Satoshi TSUTSUMI,  Yohei HASEGAWA,  Hideharu AMANO,  

[Date]2008/9/18
[Paper #]RECONF2008-34
A Case Study of Reliable Softcore Processor Using TMR Technique

Yoshihiro ICHINOMIYA,  Shiro TANOUE,  Tomoyuki ISHIDA,  Motoki AMAGASAKI,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2008/9/18
[Paper #]RECONF2008-35
A study of a fault-tolerant system using TFT method

Atsuhiro KANAMARU,  Hiroyuki KAWAI,  Yoshiki YAMAGUCHI,  Moritoshi YASUNAGA,  

[Date]2008/9/18
[Paper #]RECONF2008-36
Consideration of Combinational Circuit Mapping Method for Reconfigurable Device MPLD

Yutaro ODA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  Naoki HIRAKAWA,  Hiroaki TOGUCHI,  Masayuki SATO,  

[Date]2008/9/18
[Paper #]RECONF2008-37
複写される方へ

,  

[Date]2008/9/18
[Paper #]
Notice for photocopying

,  

[Date]2008/9/18
[Paper #]
奥付

,  

[Date]2008/9/18
[Paper #]