Information and Systems-Reconfigurable Systems(Date:2008/01/09)

Presentation
表紙

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[Date]2008/1/9
[Paper #]
目次

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[Date]2008/1/9
[Paper #]
Flex Power FPGA : An Experimental Vertically Integrated Research Project Ranging over Device, Circuit, Architecture and Software Research

Hanpei KOIKE,  

[Date]2008/1/9
[Paper #]VLD2007-105,CPSY2007-48,RECONF2007-51
High speed control system using Multilevel control circuit

Hiroaki MAEKAWA,  Ryuichi TANAKA,  Masatoshi SEKINE,  

[Date]2008/1/9
[Paper #]VLD2007-106,CPSY2007-49,RECONF2007-52
Scalable RHPC(Reconfigurable HPC) by using FPGA array

Hiroaki IIJIMA,  Kazuki SATO,  Masatoshi SEKINE,  

[Date]2008/1/9
[Paper #]VLD2007-107,CPSY2007-50,RECONF2007-53
Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs

Yuzo NISHIOKA,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2008/1/9
[Paper #]VLD2007-108,CPSY2007-51,RECONF2007-54
An optimization method of DMA transfer for the SRC-6 reconfigurable machine

Sayaka SHIDA,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2008/1/9
[Paper #]VLD2007-109,CPSY2007-52,RECONF2007-55
A Study of the Effectiveness of Dynamic Partial Reconfiguration for Size and Power Reduction

Yohei HORI,  Hirofumi SAKANE,  Kenji TODA,  

[Date]2008/1/9
[Paper #]VLD2007-110,CPSY2007-53,RECONF2007-56
Development of verification and power estimation methodology for circuits with Run Time Power Gating

Mitsutaka NAKATA,  Toshiaki SHIRAI,  Toshihiro KASHIMA,  Seidai TAKEDA,  Kimiyoshi USAMI,  Naomi SEKI,  Yohei HASEGAWA,  Hideharu AMANO,  

[Date]2008/1/9
[Paper #]VLD2007-111,CPSY2007-54,RECONF2007-57
Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating

Toshiaki SHIRAI,  Toshihiro KASHIMA,  Seidai TAKEDA,  Mitsutaka NAKATA,  Kimiyoshi USAMI,  Yohei HASEGAWA,  Naomi SEKI,  Hideharu AMANO,  

[Date]2008/1/9
[Paper #]VLD2007-112,CPSY2007-55,RECONF2007-58
An Efficient Algorithm for RTL Power Macro-modeling and Library Building

Masaaki Ohtsuki,  Masato Kawai,  Tatsuya Koyagi,  Masahiro Fukui,  

[Date]2008/1/9
[Paper #]VLD2007-113,CPSY2007-56,RECONF2007-59
Solving the Quadratic Assignment Problem by Hardware Based on a Systolic Algorithm

Yoshihiro KIMURA,  Shin'ichi WAKABAYASHI,  Shinobu NAGAYAMA,  

[Date]2008/1/9
[Paper #]VLD2007-114,CPSY2007-57,RECONF2007-60
A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation

Yosuke KAWANAKA,  Shin'ichi WAKABAYASHI,  Shinobu NAGAYAMA,  

[Date]2008/1/9
[Paper #]VLD2007-115,CPSY2007-58,RECONF2007-61
Fast calculation method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2

Hiroyuki ISHIKAWA,  Sho SHIMIZU,  Yutaka ARAKAWA,  Naoaki YAMANAKA,  Kosuke SHIBA,  

[Date]2008/1/9
[Paper #]VLD2007-116,CPSY2007-59,RECONF2007-62
A Method of Design and Update for An Address Generator Using a Hybrid Method

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2008/1/9
[Paper #]VLD2007-117,CPSY2007-60,RECONF2007-63
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[Date]2008/1/9
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[Date]2008/1/9
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[Date]2008/1/9
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