IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2007/09/13)

Presentation

表紙

[Date]2007/9/13
[Paper #]

Proposal and Application of Memory with Digit-Width Converter

Yuhki YAMABE, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2007/9/13
[Paper #]RECONF2007-15

Implementation of Memory (MPLD) with the Ability to Work as a Reconfigurable Device

Masanori YOSHIHARA, Naoki HIRAKAWA, Kazuya TANIGAWA, Tetsuo HIRONAKA, Masayuki SATO,

[Date]2007/9/13
[Paper #]RECONF2007-16

Consideration about Routing Resources for DS-HIE Architecture

Tetsuya ZUYAMA, Kazuya TANIGAWA, Tetsuo HIRONAKA,

[Date]2007/9/13
[Paper #]RECONF2007-17

Multi-context optically reconfigrable gate array

Naoki YAMAGUCHI, Minoru WATANABE,

[Date]2007/9/13
[Paper #]RECONF2007-18

A fast optical reconfiguration under an operation of a gate array in an ODRGA-VLSI

Mao NAKAJIMA, Minoru WATANABE,

[Date]2007/9/13
[Paper #]RECONF2007-19

Measuremnt for reconfiguration and retention time of a dynamic optically reconfigurable architecture

Daisaku SETO, Minoru WATANABE,

[Date]2007/9/13
[Paper #]RECONF2007-20

Reconfigurable Architecture for Car Tuners

Makoto OZONE, Katsunori HIRASE, Kazuhisa IIZUKA, Tatsuo HIRAMATSU, Shinji KIMURA,

[Date]2007/9/13
[Paper #]RECONF2007-21

A Study of Performance-driven Simultaneous Clustering and Placement for FPGA

Hiroshi SHINOHARA, Masahiro IIDA, Toshinori SUEYOSHI,

[Date]2007/9/13
[Paper #]RECONF2007-22

Hardware/Software Partitioning for SoPC based Embedded Systems

Kenichi SHIMADA, Masaru FUKUSHI, Susumu HORIGUCHI,

[Date]2007/9/13
[Paper #]RECONF2007-23

Dynamically Reconfigurable Protocol Transducer Synthesis for utilizing IPs

Yuji ISHIKAWA, Satoshi KOMATSU, Masahiro FUJITA,

[Date]2007/9/13
[Paper #]RECONF2007-24

Technology Trends in Reconfigurable Logic Circuit

Takayuki KANEDA,

[Date]2007/9/13
[Paper #]RECONF2007-25

A Study on Multibyte Processing for NFA-based Pattern Matching Circuits

Norio YAMAGAKI, Satoshi KAMIYA,

[Date]2007/9/13
[Paper #]RECONF2007-26

Pipeline MD5 Implementations on FPGA with Data Forwarding

Anh Tuan HOANG, Katsuhiro YAMAZAKI, Shigeru OYANAGI,

[Date]2007/9/13
[Paper #]RECONF2007-27

Performance Evaluation of Dynamic-Reconfigurable Processor MuCCRA-1 with various applications

Adpu PARIMALA, Yohei HASEGAWA, Vasutan TANBUNHENG, Hideharu AMANO,

[Date]2007/9/13
[Paper #]RECONF2007-28

Dynamically Reconfigurable Processor with Direct Execution Mode

Toru SANO, Yohei HASEGAWA, Satoshi TSUTSUMI, Hideharu AMANO,

[Date]2007/9/13
[Paper #]RECONF2007-29

Representing Dynamically Reconfigurable Architectures for Placement and Routing based on Graph with Configuration Information

Vasutan TUNBUNHENG, Yohei HASEGAWA, Satoshi TSUTSUMI, Masaru KATO, Hideharu AMANO,

[Date]2007/9/13
[Paper #]RECONF2007-30

An Energy Reduction Technique with Dynamic Frequency Scaling for Dynamically Reconfigurable Processor Arrays

Satoshi TSUTSUMI, Yohei HASEGAWA, Takashi NISHIMURA, Hideharu AMANO,

[Date]2007/9/13
[Paper #]RECONF2007-31

複写される方へ

[Date]2007/9/13
[Paper #]