Information and Systems-Reconfigurable Systems(Date:2005/05/05)

Presentation
目次

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[Date]2005/5/5
[Paper #]
A Reconfigurable Embedded Decompressor for LSI Testing

Tomoyuki SAIKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2005/5/5
[Paper #]RECONF2005-1
Development of clustering tool to reduce area of chip and delay

Masaki KOBATA,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2005/5/5
[Paper #]RECONF2005-2
Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure

Ittetsu TANIGUCHI,  Kyoko UEDA,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2005/5/5
[Paper #]RECONF2005-3
Implementation of an SMT Processor and its Reconfigurable Cache with FPGA

Yoshiyasu OGASAWARA,  Norito KATO,  Masanori YAMATO,  Mikiko SATO,  Koichi SASADA,  Kaname UCHIKURA,  Mitaro NAMIKI,  Hironori NAKAJO,  

[Date]2005/5/5
[Paper #]RECONF2005-4
Improvement of Signature-based Phase Detection and its Application to Power Reduction in Caches

YUYA UENO,  LUONG D. HUNG,  MASANORI TAKADA,  DAISUKE TASHIRO,  SHUICHI SAKAI,  

[Date]2005/5/5
[Paper #]RECONF2005-5
A general view on VLSI design methodology

Yukihiro Nakamura,  

[Date]2005/5/5
[Paper #]RECONF2005-6
Design of a Heap-tree Based Scalable Stochastic Biochemical Simulator on an FPGA

Masato YOSHIMI,  Yasunori OSANA,  Yow IWAOKA,  Tomonori FUKUSHIMA,  Akira HUNAHASHI,  Noriko HIROI,  Yuichiro SHIBATA,  Naoki IWANAGA,  Hiroaki KITANO,  Hideharu AMANO,  

[Date]2005/5/5
[Paper #]RECONF2005-7
Scheduling of Rate Law Functions for an FPGA-based Biochemical Simulator

Naoki IWANAGA,  Yuichiro SHIBATA,  Masato YOSHIMI,  Yasunori OSANA,  Yow IWAOKA,  Tomonori FUKUSHIMA,  Hideharu AMANO,  Akira FUNAHASHI,  Noriko HIROI,  Hiroaki KITANO,  Kiyoshi OGURI,  

[Date]2005/5/5
[Paper #]RECONF2005-8
Implementation and Evaluation of Numerical Integrators on ReCSiP

Yasunori OSANA,  Masato YOSHIMI,  Yow IWAOKA,  Akira FUNAHASHI,  Noriko HIROI,  Yuichiro SHIBATA,  Naoki IWANAGA,  Hiroaki KITANO,  Hideharu AMANO,  

[Date]2005/5/5
[Paper #]RECONF2005-9
Analysis of Operating Speed and Power Consumption In Flex Power FPGA : From Circuit Level To Chip Level

Masakazu Hioki,  Takashi Kawanami,  Toshiyuki Tsutsumi,  Tadashi Nakagawa,  Toshihiro Sekigawa,  Hanpei Koike,  

[Date]2005/5/5
[Paper #]RECONF2005-10
Area Overhead Estimation for Vth Control in Flex Power FPGA

Takashi KAWANAMI,  Masakazu HIOKI,  Toshiyuki TSUTSUMI,  Tadashi NAKAGAWA,  Toshihiro SEKIGAWA,  Hanpei KOIKE,  

[Date]2005/5/5
[Paper #]RECONF2005-11
Reducing the Delay by Using the Small-World Network Structure

Hisashi TSUKIASHI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2005/5/5
[Paper #]RECONF2005-12
Code Scheduling in Consideration of Place and Route in Back End Compiler for PARS

Ryuji HADA,  Takeshi TAKEUCHI,  Takeshi FUKUDA,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2005/5/5
[Paper #]RECONF2005-13
A Simulation Platform for Evaluating Granularity of Self-Reconfigurable Device

Shinichi KOUYAMA,  Futoshi MORIE,  Kentaro NAKAHARA,  Tomonori IZUMI,  Hiroyuki OCHI,  Yukihiro NAKAMURA,  

[Date]2005/5/5
[Paper #]RECONF2005-14
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[Date]2005/5/5
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[Date]2005/5/5
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[Date]2005/5/5
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